SLVS667B July   2006  – January 2016 TPS65022

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 7.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 7.3.3  Power Save Mode Operation
      4. 7.3.4  Low Ripple Mode
      5. 7.3.5  Soft-Start
      6. 7.3.6  100% Duty Cycle Low Dropout Operation
      7. 7.3.7  Active Discharge When Disabled
      8. 7.3.8  Power Good Monitoring
      9. 7.3.9  Low Dropout Voltage Regulators
      10. 7.3.10 Undervoltage Lockout
      11. 7.3.11 Power-Up Sequencing
      12. 7.3.12 System Reset + Control Signals
        1. 7.3.12.1 DEFLDO1 and DEFLDO2
        2. 7.3.12.2 Interrupt Management and the INT Pin
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 VERSION Register Address: 00h (read only)
      2. 7.6.2 PGOODZ Register Address: 01h (read only)
      3. 7.6.3 MASK Register Address: 02h (read/write) Default Value: C0h
      4. 7.6.4 REG_CTRL Register Address: 03h (read/write) Default Value: FFh
      5. 7.6.5 CON_CTRL Register Address: 04h (read/write) Default Value: B1h
      6. 7.6.6 CON_CTRL2 Register Address: 05h (read/write) Default Value: 40h
      7. 7.6.7 DEFCORE Register Address: 06h (read/write) Default Value: 14h/1Eh
      8. 7.6.8 DEFSLEW Register Address: 07h (read/write) Default Value: 06h
      9. 7.6.9 LDO_CTRL Register Address: 08h (read/write) Default Value: set with DEFLDO1 and DEFLDO2
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Voltage Connection
      2. 8.1.2 Unused Regulators
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the DC-DC Converters
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Voltage Selection
        5. 8.2.2.5 VRTC Output
        6. 8.2.2.6 LDO1 and LDO2
        7. 8.2.2.7 TRESPWRON
        8. 8.2.2.8 VCC-Filter
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7 Detailed Description

7.1 Overview

TPS65022 has 5 regulator channels, 3 DCDCs and 2 LDOs. DCDC3 has dynamic voltage scaling feature, DVS, that allows for power reduction to CORE supplies during idle operation or over voltage during heavy duty operation. With DVS and 2 more DCDCs plus 2 LDOs, the TPS65022 is ideal for CORE, Memory, IO, and peripheral power for the entire system of a wide range of suitable applications.

The device incorporates enables for the DCDCs and LDOs, I2C for device control, pushbutton and a reset interface that complete the system and allow for the TPS65022 to be adapted for different kinds of processors or FPGAs.

For noise sensitive circuits, the DCDCs can be synchronized out of phase from one another, reducing the peak noise at the switching frequency. Each converter can be forced to operate in PWM mode to ensure constant switching frequency across the entire load range. However, for low load efficiency performance the DCDCs automatically enter PSM mode, which reduces the switching frequency when the load current is low, saving power at idle operation.

7.2 Functional Block Diagram

TPS65022 fbd_lvs613.gif

7.3 Feature Description

7.3.1 VRTC Output and Operation With or Without Backup Battery

The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail. This is the VCC_BATT rail of the Intel® PXA270 Bulverde processor for example.

In applications using a backup battery, the backup voltage can be either directly connected to the TPS65022 VBACKUP pin if a Li-Ion cell is used, or through a boost converter (TPS61070) if a single NiMH battery is used. The voltage applied to the VBACKUP pin is fed through a PMOS switch to the VRTC pin. The TPS65022 asserts the RESPWRON signal if VRTC drops below 2.4 V. This, together with 375 mV at 30 mA drop out for the PMOS switch means that the voltage applied at VBACKUP must be greater than 2.775 V for normal system operation.

When the voltage at the VSYSIN pin exceeds 2.65 V, the path from VBACKUP to VRTC is cut, and VRTC is supplied by a similar PMOS switch from the voltage source connected to the VSYSIN input. Typically this is the VDCDC1 converter but can be any voltage source within the appropriate range.

In systems where no backup battery is used, the VBACKUP pin is connected to GND. In this case, a low power LDO is enabled, supplied from VCC and capable of delivering 30 mA to the 3-V output. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V. VRTC is then supplied from the external source connected to this pin as previously described.

Inside TPS65022 there is a switch (Vmax switch) that selects the higher voltage between VCC and VBACKUP. This is used as the supply voltage for some basic functions. The functions powered from the output of the Vmax switch are:

  • INT output
  • RESPWRON output
  • HOT_RESET input
  • LOW_BATT output
  • PWRFAIL output
  • Enable pins for DC-DC converters, LDO1 and LDO2
  • Undervoltage lockout comparator (UVLO)
  • Reference system with low frequency timing oscillators
  • LOW_BATT and PWRFAIL comparators

The main 1.5-MHz oscillator, and the I2C interface are only powered from VCC.

TPS65022 vrtc_sch_lvs607.gif
V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%
RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%
Figure 28. RTC and nRESPWRON

7.3.2 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3

The TPS65022 incorporates three synchronous step-down converters operating typically at 1.5-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter the power save mode (PSM), and operate with pulse frequency modulation (PFM). The VDCDC1 converter is capable of delivering 1.2-A output current, the VDCDC2 converter is capable of delivering 1 A and the VDCDC3 converter is capable of delivering up to 900 mA.

The converter output voltages can be programmed by the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The VDCDC1 converter defaults to 3 V or 3.3 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1 is tied to ground, the default is 3 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See the application information section for more details.

The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin. If DEFDCDC2 is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 2.5 V. When the DEFDCDC2 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.

The VDCDC3 converter defaults to 1.3 V or 1.55 V depending on the DEFDCDC3 configuration pin. If DEFDCDC3 is tied to ground the default is 1.3 V. If it is tied to VCC, the default is 1.55 V. When the DEFDCDC3 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V. The core voltage can be reprogrammed through the serial interface in the range of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst any programmed voltage change is underway, whether the voltage is being increased or decreased. The DEFCORE and DEFSLEW registers are used to program the output voltage and slew rate during voltage transitions.

The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs of which are available through the serial interface. The outputs of the DC-DC converters can be optionally discharged through on-chip 300-Ω resistors when the DC-DC converters are disabled.

During PWM operation, the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch.

The three DC-DC converters operate synchronized to each other with the VDCDC1 converter as the master. A 180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3 switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the VDCDC2 converter from 3.7 V to 2.5 V, and the VDCDC3 converter from 3.7 V to 1.5 V. The phase of the three converters can be changed using the CON_CTRL register.

7.3.3 Power Save Mode Operation

As the load current decreases, the converters enter the power save mode operation. During PSM, the converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 1.5 MHz, nominal for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency.

In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM is calculated as follows:

Equation 1. TPS65022 q1_ipfmdcdc_lvs607.gif

During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter effectively delivers a constant current defined as follows.

Equation 2. TPS65022 q2_ipfm2_lvs607.gif

If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode if either of the following conditions are met:

  1. the output voltage drops 2% below the nominal VO due to increasing load current
  2. the PFM burst time exceeds 16 × 1/fs (10.67 μs typical).

These control methods reduce the quiescent current to typically 14 μA per converter, and the switching activity to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM mode.

7.3.4 Low Ripple Mode

Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the DC-DC converters if operated in PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is reduced, depending on the actual load current. The lower the actual output current on the converter, the lower the output ripple voltage. For an output current above 10 mA, there is only a minor difference in output voltage ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is used to keep the switching frequency above the audible range in PFM mode down to a low output current.

7.3.5 Soft-Start

Each of the three converters has an internal soft-start circuit that limits the inrush current during start-up. The soft start is realized by using a very low current to initially charge the internal compensation capacitor. The soft start time is typically 750 μs if the output voltage ramps from 5% to 95% of the final target value. If the output is already pre-charged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a short delay of typically 170 μs between the converter being enabled and switching activity actually starting. This is to allow the converter to bias itself properly, to recognize if the output is pre-charged, and if so to prevent discharging of the output while the internal soft start ramp catches up with the output voltage.

7.3.6 100% Duty Cycle Low Dropout Operation

The TPS65022 converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load current and output voltage. It is calculated as:

Equation 3. VIN(min) = VOUT(min) + IOUT(max) × (rDS(on)max + RL)

where

  • IOUT(max) = maximum load current (Note: ripple current in the inductor is zero under these conditions)
  • rDS(on)max = maximum P-channel switch rDS(on)
  • RL = DC resistance of the inductor
  • VOUT(min) = nominal output voltage minus 2% tolerance limit

7.3.7 Active Discharge When Disabled

When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled through the CON_CTRL2 register in the serial interface. When this feature is enabled, the VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300 Ω (typical) load which is active as long as the converters are disabled.

7.3.8 Power Good Monitoring

All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5% hysteresis. The outputs of these comparators are available in the PGOODZ register through the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are disabled and the relevant PGOODZ register bits indicate that power is good.

7.3.9 Low Dropout Voltage Regulators

The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors, with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the LDO_EN pin, both LDOs can be disabled or programmed through the serial interface using the REG_CTRL and LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect external regulators in parallel in systems with a backup battery. The TPS65022 step-down and LDO voltage regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the junction temperature rises above 160°C.

7.3.10 Undervoltage Lockout

The undervoltage lockout circuit for the five regulators on the TPS65022 prevents the device from malfunctioning at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note that when any of the DC-DC converters are running, there is an input current at the VCC pin, which is up to 3 mA when all three converters are running in PWM mode. This current must be taken into consideration if an external RC filter is used at the VCC pin to remove switching noise from the TPS65022 internal analog circuitry supply.

7.3.11 Power-Up Sequencing

The TPS65022 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The relevant control pins are described in Table 2.

Table 2. Control Pins and Status Outputs for DC-DC Converters

PIN NAME INPUT OUTPUT FUNCTION
DEFDCDC3 I Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.3 V, DEFDCDC3 = VCC defaults VDCDC3 to 1.55 V.
DEFDCDC2 I Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5 V.
DEFDCDC1 I Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 3 V, DEFDCDC1 = VCC defaults VDCDC1 to 3.3 V.
DCDC3_EN I Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter
DCDC2_EN I Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter
DCDC1_EN I Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter
HOT_RESET I The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any TPS65022 settings except the output voltage of VDCDC3. Activating HOT_RESET sets the voltage of VDCDC3 to its default value defined with the DEFDCDC3 pin. HOT_RESET is internally de-bounced by the TPS65022.
RESPWRON O RESPWRON is held low when power is initially applied to the TPS65022. The VRTC voltage is monitored: RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.
TRESPWRON I Connect a capacitor here to define the RESET time at the RESPWRON pin. 1 nF typically gives 100 ms.

7.3.12 System Reset + Control Signals

The RESPWRON signal can be used as a global reset for the application. It is an open-drain output. The RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.

The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV) hysteresis.

The DCDC3 converter is reset to its default output voltage defined by the DEFDCDC3 input, when HOT_RESET is asserted. Other I2C registers are not affected. Generally, the DCDC3 converter is set to its default voltage with one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout (UVLO) condition, RESPWRON active, both DCDC3-converter AND DCDC1-converter disabled. In addition, the voltage of VDCDC3 changes to 1xxx0, if the VDCDC1 converter is disabled. Where xxx is the state before VDCDC1 was disabled.

7.3.12.1 DEFLDO1 and DEFLDO2

These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of both LDOs can be changed during operation with the I2C interface as described in the interface description.

Table 3. LDO1 and LDO2 Default Voltage Options

DEFLDO2 DEFLDO1 VLDO1 VLDO2
0 0 1.1 V 1.3 V
0 1 1.5 V 1.3 V
1 0 2.6 V 2.8 V
1 1 3.15 V 3.3 V

7.3.12.2 Interrupt Management and the INT Pin

The INT pin combines the outputs of the PGOOD comparators from each DC-DC converter and LDOs. The INT pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register is read through the serial interface, any active bits are then blocked from the INT output pin.

Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO interrupts since this provides the POWER_OK function.

7.4 Device Functional Modes

The TPS650231 device is in the ON or the OFF mode. The OFF mode is entered when the voltage on VCC is below the UVLO threshold, 2.35 V (typically). Once the voltage at V CC has increased above UVLO, the device enters ON mode. In the ON mode, the DCDCs and LDOs are available for use.

7.5 Programming

7.5.1 Serial Interface

The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS65022 has a 7-bit address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from the register addresses not listed in this section results in FFh being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65022 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65022 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65022 device must leave the data line high to enable the master to generate the stop condition.

TPS65022 bit_trns_time_lvs607.gif Figure 29. Bit Transfer on the Serial Interface
TPS65022 st_sp_time_lvs07.gif Figure 30. START and STOP Conditions
TPS65022 ser_if_write_lvs613.gif Figure 31. Serial Interface WRITE to TPS65022 Device
TPS65022 ser_if_a_read_lvs613.gif Figure 32. Serial Interface READ from TPS65022: Protocol A
TPS65022 ser_if_b_read_lvs613.gif Figure 33. Serial Interface READ from TPS65022: Protocol B
TPS65022 ser_if_time_lvs607.gif Figure 34. Serial Interface Timing Diagram

7.6 Register Maps

7.6.1 VERSION Register Address: 00h (read only)

Table 4. VERSION Register

VERSION B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function 0 0 1 0 0 0 1 0
Read/Write R R R R R R R R

7.6.2 PGOODZ Register Address: 01h (read only)

Table 5. PGOODZ Register

PGOODZ B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function PWRFAILZ LOWBATTZ PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
Set by signal PWRFAIL LOWBATT PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
VDCDC3
PGOODZ
LDO2
PGOODZ
LDO1
Default value loaded by: PWRFAILZ LOWBATTZ PGOOD
VDCDC1
PGOOD
VDCDC2
PGOOD
VDCDC3
PGOOD
LDO2
PGOOD
LDO1
Read/Write R R R R R R R R
Bit 7 PWRFAILZ:
0 = indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold
1 = indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold
Bit 6 LOWBATTZ:
0 = indicates that the LOWBATT_SNS input voltage is above the 1-V threshold
1 = indicates that the LOWBATT_SNS input voltage is below the 1-V threshold
Bit 5 PGOODZ VDCDC1:
0 = indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if the VDCDC1 converter is disabled.
1 = indicates that the VDCDC1 converter output voltage is below its target regulation voltage
Bit 4 PGOODZ VDCDC2:
0 = indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if the VDCDC2 converter is disabled.
1 = indicates that the VDCDC2 converter output voltage is below its target regulation voltage
Bit 3 PGOODZ VDCDC3: .
0 = indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if the VDCDC3 converter is disabled and during a DVM controlled output voltage transition.
1 = indicates that the VDCDC3 converter output voltage is below its target regulation voltage
Bit 2 PGOODZ LDO2:
0 = indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is disabled.
1 = indicates that LDO2 output voltage is below its target regulation voltage
Bit 1 PGOODZ LDO1
0 = indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is disabled.
1 = indicates that the LDO1 output voltage is below its target regulation voltage

7.6.3 MASK Register Address: 02h (read/write) Default Value: C0h

Table 6. MASK Register

MASK B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function MASK
PWRFAILZ
MASK
LOWBATTZ
MASK
VDCDC1
MASK
VDCDC2
MASK
VDCDC3
MASK
LDO2
MASK
LDO1
Default 1 1 0 0 0 0 0 0
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/Write R/W R/W R/W R/W R/W R/W R/W

The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1 masks PGOODZ<n>.

7.6.4 REG_CTRL Register Address: 03h (read/write) Default Value: FFh

The REG_CTRL register is used to disable or enable the power supplies through the serial interface. The contents of the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The REG_CTRL bits are automatically reset to default when the corresponding enable pin is low.

Table 7. REG_CTRL Register

REG_CTRL B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function VDCDC1 ENABLE VDCDC2 ENABLE VDCDC3 ENABLE LDO2
ENABLE
LDO1
ENABLE
Default 1 1 1 1 1 1 1 1
Set by signal DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ LDO_ENZ LDO_ENZ
Default value loaded by: UVLO UVLO UVLO UVLO UVLO
Read/Write R/W R/W R/W R/W R/W
Bit 5 VDCDC1 ENABLE
DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when DCDC1_EN returns high.
Bit 4 VDCDC2 ENABLE
DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when DCDC2_EN returns high.
Bit 3 VDCDC3 ENABLE
DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when DCDC3_EN returns high.
Bit 2 LDO2 ENABLE
LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high.
Bit 1 LDO1 ENABLE
LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high.

7.6.5 CON_CTRL Register Address: 04h (read/write) Default Value: B1h

Table 8. CON_CTRL Register

CON_CTRL B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function DCDC2
PHASE1
DCDC2
PHASE0
DCDC3
PHASE1
DCDC3
PHASE0
LOW
RIPPLE
FPWM
DCDC2
FPWM
DCDC1
FPWM
DCDC3
Default 1 0 1 1 0 0 0 1
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is taken as the reference and consequently has a fixed zero phase shift.

Table 9. DCDC2 and DCDC3 Phase Delay

CON_CTRL<7:6> DCDC2 CONVERTER
DELAYED BY
CON_CTRL<5:4> DCDC3 CONVERTER
DELAYED BY
00 zero 00 zero
01 1/4 cycle 01 1/4 cycle
10 1/2 cycle 10 1/2 cycle
11 3/4 cycle 11 3/4 cycle
Bit 3 LOW RIPPLE:
0 = PFM mode operation optimized for high efficiency for all converters
1 = PFM mode operation optimized for low output voltage ripple for all converters
Bit 2 FPWM DCDC2:
0 = DCDC2 converter operates in PWM / PFM mode
1 = DCDC2 converter is forced into fixed frequency PWM mode
Bit 1 FPWM DCDC1:
0 = DCDC1 converter operates in PWM / PFM mode
1 = DCDC1 converter is forced into fixed frequency PWM mode
Bit 0 FPWM DCDC3:
0 = DCDC3 converter operates in PWM / PFM mode
1 = DCDC3 converter is forced into fixed frequency PWM mode

7.6.6 CON_CTRL2 Register Address: 05h (read/write) Default Value: 40h

Table 10. CON_CTRL2 Register

CON_CTRL2 B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function GO Core adj
allowed
DCDC2
discharge
DCDC1
discharge
DCDC3
discharge
Default 0 1 0 0 0 0 0 0
Default value loaded by: UVLO +
DONE
RESET(1) UVLO UVLO UVLO
Read/Write R/W R/W R/W R/W R/W

The CON_CTRL2 register can be used to take control the inductive converters.

RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:

  • undervoltage lockout (UVLO)
  • DCDC1_EN and DCDC3_EN pulled low
  • HOT_RESET pulled low
  • RESPWRON active
  • VRTC below threshold

Bit 7 GO:
0 = no change in the output voltage for the DCDC3 converter
1 = the output voltage of the DCDC3 converter is changed to the value defined in DEFCORE with the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is complete. The transition is considered complete in this case when the desired output voltage code has been reached, not when the VDCDC3 output voltage is actually in regulation at the desired voltage.
Bit 6 CORE ADJ Allowed:
0 = the output voltage is set with the I2C register
1 = DEFDCDC3 is either connected to GND or VCC or an external voltage divider. When connected to GND or VCC, VDCDC3 defaults to 1.3 V or 1.55 V respectively at start-up.
Bit 2– 0 0 = the output capacitor of the associated converter is not actively discharged when the converter is disabled
1 = the output capacitor of the associated converter is actively discharged when the converter is disabled. This decreases the fall time of the output voltage at light load.

7.6.7 DEFCORE Register Address: 06h (read/write) Default Value: 14h/1Eh

Table 11. DEFCORE Register

DEFCORE B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function CORE4 CORE3 CORE2 CORE1 CORE0
Default 0 0 0 1 DEFDCDC3 1 DEFDCDC3 0
Default value loaded by: RESET(2) RESET(1) RESET(1) RESET(1) RESET(2)
Read/Write R/W R/W R/W R/W R/W

RESET(1): DEFCORE[3:1] are reset to the default value by one of these events:

  • undervoltage lockout (UVLO)
  • DCDC1_EN and DCDC3_EN pulled low
  • HOT_RESET pulled low
  • RESPWRON active
  • VRTC below threshold

RESET(2): DEFCORE[4] and DEFCORE[0] are reset to the default value by one of these events:

  • undervoltage lockout (UVLO)
  • DCDC1_EN pulled low
  • HOT_RESET pulled low
  • RESPWRON active
  • VRTC below threshold

Table 12. DCDC3 DVS Voltages

CORE4 CORE3 CORE2 CORE1 CORE0 VDCDC3 CORE4 CORE3 CORE2 CORE1 CORE0 VDCDC3
0 0 0 0 0 0.8 V 1 0 0 0 0 1.2 V
0 0 0 0 1 0.825 V 1 0 0 0 1 1.225 V
0 0 0 1 0 0.85 V 1 0 0 1 0 1.25 V
0 0 0 1 1 0.875 V 1 0 0 1 1 1.275 V
0 0 1 0 0 0.9 V 1 0 1 0 0 1.3 V
0 0 1 0 1 0.925 V 1 0 1 0 1 1.325 V
0 0 1 1 0 0.95 V 1 0 1 1 0 1.35 V
0 0 1 1 1 0.975 V 1 0 1 1 1 1.375 V
0 1 0 0 0 1 V 1 1 0 0 0 1.4 V
0 1 0 0 1 1.025 V 1 1 0 0 1 1.425 V
0 1 0 1 0 1.05 V 1 1 0 1 0 1.45 V
0 1 0 1 1 1.075 V 1 1 0 1 1 1.475 V
0 1 1 0 0 1.1 V 1 1 1 0 0 1.5 V
0 1 1 0 1 1.125 V 1 1 1 0 1 1.525 V
0 1 1 1 0 1.15 V 1 1 1 1 0 1.55 V
0 1 1 1 1 1.175 V 1 1 1 1 1 1.6 V

7.6.8 DEFSLEW Register Address: 07h (read/write) Default Value: 06h

Table 13. DEFSLEW Register

DEFSLEW B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function SLEW2 SLEW1 SLEW0
Default 1 1 0
Default value loaded by: UVLO UVLO UVLO
Read/Write R/W R/W R/W

Table 14. DCDC3 DVS Slew Rate

SLEW2 SLEW1 SLEW0 VDCDC3 SLEW RATE
0 0 0 0.15 mV/μs
0 0 1 0.3 mV/μs
0 1 0 0.6 mV/μs
0 1 1 1.2 mV/μs
1 0 0 2.4 mV/μs
1 0 1 4.8 mV/μs
1 1 0 9.6 mV/μs
1 1 1 Immediate

7.6.9 LDO_CTRL Register Address: 08h (read/write) Default Value: set with DEFLDO1 and DEFLDO2

Table 15. LDO_CTRL Register

LDO_CTRL B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function LDO2_2 LDO2_1 LDO2_0 LDO1_2 LDO1_1 LDO1_0
Default DEFLDOx DEFLDOx DEFLDOx DEFLDOx DEFLDOx DEFLDOx
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO
Read/Write R/W R/W R/W R/W R/W R/W

The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2.

The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 3.

Table 16. LDO1 and LDO2 I2C Voltage Options

LDO1_2 LDO1_1 LDO1_0 LDO1 OUTPUT
VOLTAGE
LDO2_2 LDO2_1 LDO2_0 LDO2 OUTPUT
VOLTAGE
0 0 0 1 V 0 0 0 1.05 V
0 0 1 1.1 V 0 0 1 1.2 V
0 1 0 1.35 V 0 1 0 1.3 V
0 1 1 1.5 V 0 1 1 1.8 V
1 0 0 2.2 V 1 0 0 2.5 V
1 0 1 2.6 V 1 0 1 2.8 V
1 1 0 2.85 V 1 1 0 3 V
1 1 1 3.15 V 1 1 1 3.3 V