SLVSBG2A September   2013  – June 2016 TPS65154

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Simplified System Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Linear Regulator (VCC)
        1. 5.3.1.1 Power-Up (Linear Regulator)
        2. 5.3.1.2 Power-Down (Linear Regulator)
        3. 5.3.1.3 Protection (Linear Regulator)
      2. 5.3.2  Boost Converter 1 (AVDD)
        1. 5.3.2.1 Power-Up (Boost Converter 1)
        2. 5.3.2.2 Power-Down (Boost Converter 1)
        3. 5.3.2.3 Protection (Boost Converter 1)
      3. 5.3.3  Boost Converter 2 (VGH)
        1. 5.3.3.1 Power-Up (Boost Converter 2)
        2. 5.3.3.2 Power-Down (Boost Converter 2)
        3. 5.3.3.3 Protection (Boost Converter 2)
      4. 5.3.4  Negative Charge Pump (VGL)
        1. 5.3.4.1 Power-Up (Negative Charge Pump)
        2. 5.3.4.2 Power-Down (Negative Charge Pump)
        3. 5.3.4.3 Protection (Negative Charge Pump)
      5. 5.3.5  Gate Voltage Shaping
      6. 5.3.6  Panel Discharge (XAO)
      7. 5.3.7  Reset Generator (RST)
      8. 5.3.8  Programmable VCOM
        1. 5.3.8.1 Operational Amplifier Performance
        2. 5.3.8.2 Power-Up (Programmable VCOM)
        3. 5.3.8.3 Power-Down (Programmable VCOM)
      9. 5.3.9  WLED Driver
        1. 5.3.9.1 WLED Boost Converter
        2. 5.3.9.2 Current Sinks
        3. 5.3.9.3 Protection
        4. 5.3.9.4 Enable and Start-Up
      10. 5.3.10 Undervoltage Lockout
    4. 5.4 Device Functional Modes
      1. 5.4.1 Dimming Modes
        1. 5.4.1.1 Direct Dimming
        2. 5.4.1.2 Phase-Shift Dimming
      2. 5.4.2 Power Sequencing
        1. 5.4.2.1 Power-Up
        2. 5.4.2.2 Power-Down
    5. 5.5 Programming
      1. 5.5.1 Configuration
        1. 5.5.1.1 General
          1. 5.5.1.1.1 I2C Interface
          2. 5.5.1.1.2 Slave Addresses
          3. 5.5.1.1.3 Write Protect
      2. 5.5.2 Programming Examples (Excluding VCOM)
        1. 5.5.2.1 Writing to a Single RAM Register
        2. 5.5.2.2 Writing to Multiple RAM Registers
        3. 5.5.2.3 Saving Contents of all RAM Registers to EEPROM
        4. 5.5.2.4 Reading from a Single RAM Register
        5. 5.5.2.5 Reading from a Single EEPROM Register
        6. 5.5.2.6 Reading from Multiple RAM Registers
        7. 5.5.2.7 Reading from Multiple EEPROM Registers
      3. 5.5.3 Programming Examples - VCOM
        1. 5.5.3.1 Writing a VCOM Value of 77h to WR
        2. 5.5.3.2 Writing a VCOM Value of 77h to IVR and WR
        3. 5.5.3.3 Reading a VCOM Value of 77h from WR
        4. 5.5.3.4 Reading a VCOM Value of 77h from IVR
    6. 5.6 Register Map
      1. 5.6.1 Configuration Registers (Excluding VCOM)
        1. 5.6.1.1  CONFIG (00h)
        2. 5.6.1.2  VCC (01h)
        3. 5.6.1.3  DLY1 (02h)
        4. 5.6.1.4  AVDD (03h)
        5. 5.6.1.5  FSW1 (04h)
        6. 5.6.1.6  SS2 (05h)
        7. 5.6.1.7  DLY2 (06h)
        8. 5.6.1.8  VGL (07h)
        9. 5.6.1.9  SS3 (08h)
        10. 5.6.1.10 DLY3 (09h)
        11. 5.6.1.11 VGH (0Ah)
        12. 5.6.1.12 SS4 (0Bh)
        13. 5.6.1.13 FSW3 (0Ch)
        14. 5.6.1.14 DLY4 (0Dh)
        15. 5.6.1.15 OVP (0Eh)
        16. 5.6.1.16 FDIM (OFh)
        17. 5.6.1.17 RESET (10h)
        18. 5.6.1.18 VDET (11h)
        19. 5.6.1.19 DLY6 (12h)
        20. 5.6.1.20 VMAX (13h)
        21. 5.6.1.21 VMIN (14h)
        22. 5.6.1.22 USER (15h)
        23. 5.6.1.23 CONTROL (FFh)
      2. 5.6.2 VCOM Registers
        1. 5.6.2.1 VCOM DATA (Slave Address 28h, Register Address 00h)
        2. 5.6.2.2 VCOM CONTROL (Slave Address 28h, Register Address 02h)
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 External Component Selection
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Detailed Description

5.1 Overview

The TPS65154 device integrates the bias and backlight functions needed by an active matrix liquid crystal display.

The LCD bias functions comprise

  • A synchronous boost converter to generate AVDD
  • A non-synchronous boost converter to generate VGH
  • An inverting charge pump to generate VGL
  • An low dropout linear regulator to generate VCC
  • A gate-voltage shaping function
  • A programmable VCOM buffer
  • XAO and RST signals
  • An I2C programming interface

The backlight driver functions comprise

  • A non-synchronous boost converter
  • A six-channel WLED driver with PWM dimming

The device configuration is stored in an on-chip nonvolatile memory, which can be programmed via an I2C interface.

5.2 Functional Block Diagram

Figure 5-1 shows a top-level block diagram of the TPS65154.

TPS65154 FBD_01_SLVSBG2.gif Figure 5-1 Top-Level Block Diagram

5.3 Feature Description

The following sections describe the features of the TPS65154.

5.3.1 Linear Regulator (VCC)

The linear regulator is supplied directly from the VIN pin, and its output voltage can be programmed to 1.0 V, 1.2 V, 1.89 V, or 2.5 V using the VCC register.

TPS65154 G502_SLVSBG2.gif Figure 5-2 Linear Regulator Block Diagram

5.3.1.1 Power-Up (Linear Regulator)

The linear regulator starts tDLY1 milliseconds after the supply voltage exceeds the undervoltage lockout threshold (VIN > VUVLO). It does not have a soft-start function, and its output ramps up as fast as the supply voltage slew rate and the linear regulator's output capacitance allow.

5.3.1.2 Power-Down (Linear Regulator)

The linear regulator is turned off as soon as the supply voltage falls below the undervoltage lockout threshold (VIN < VUVLO). VCC is actively discharged during power-down.

5.3.1.3 Protection (Linear Regulator)

The linear regulator is protected against short-circuits and undervoltage conditions. An undervoltage condition is detected if the linear regulator's output falls below 70% of its programmed voltage for longer than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the linear regulator's output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-circuit detection has no time delay associated with it). To recover normal operation following either an undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR applied.

5.3.2 Boost Converter 1 (AVDD)

Boost converter 1 is synchronous and uses a virtual current mode topology that:

  • achieves high efficiencies;
  • allows the converter to work in continuous conduction mode under all operating conditions, simplifying compensation; and
  • provides true input-output isolation when the boost converter is disabled.
TPS65154 G503_SLVSBG2.gif Figure 5-3 Boost Converter 1 Internal Block Diagram

Boost converter 1's switching frequency can be programmed to 400 kHz, 600 kHz, 800 kHz, or 1 MHz using the FSW1 register. Its output voltage can be programmed from 6.5 V to 9.6 V in 100 mV steps using the AVDD register.

Boost converter 1 uses an external compensation network connected to the COMP1 pin to stabilize its feedback loop. A simple series R-C network connected between the COMP1 pin and ground is sufficient to achieve good performance, that is, stable and with good transient response. Good starting values, which will work for most applications, are 25 kΩ and 3.9 nF.

In some applications (for example, those using electrolytic output capacitors), it may be necessary to include a second compensation capacitor between the COMP1 pin and ground. This has the effect of adding an additional pole in the feedback loop's frequency response, which cancels the zero introduced by the output capacitor's ESR.

The synchronous topology of boost converter 1 ensures that AVDD is fully isolated from VIN when the converter is disabled.

5.3.2.1 Power-Up (Boost Converter 1)

Boost converter 1 starts tDLY2 milliseconds after RST goes high. Delay time tDLY2 can be programmed from 0 ms to 75 ms using the DLY2 register.

To minimize inrush current during start-up, boost converter 1 ramps its output voltage in tSS2 milliseconds. Start-up time tSS2 can be programmed from 0.5 ms to 75 ms using the SS2 register. Longer soft-start times generate lower inrush currents.

5.3.2.2 Power-Down (Boost Converter 1)

Boost converter 1 is disabled when VIN<VUVLO. When disabled, boost converter 2 actively discharges AVDD by turning on Q2.

5.3.2.3 Protection (Boost Converter 1)

Boost converter 1 is protected against short-circuits and undervoltage conditions. An undervoltage condition is detected if the boost converter's output falls below 70% of its programmed voltage for longer than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the boost converter's output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-circuit detection has no time delay associated with it). To recover normal operation following either an undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR applied.

5.3.3 Boost Converter 2 (VGH)

Boost converter 2 is non-synchronous and uses a constant off-time topology. The converter's switching frequency is not constant but adapts itself to VIN and VGH. Boost converter 2 uses peak current control and is designed to operate permanently in discontinuous conduction mode (DCM), thereby allowing the internal compensation circuit to achieve stable operation over a wide range of output voltages and currents. Boost converter 2's output voltage can be programmed from 18 V to 25.5 V using the VGH register.

TPS65154 G504_SLVSBG2.gif Figure 5-4 Boost Converter 2 Block Diagram

5.3.3.1 Power-Up (Boost Converter 2)

Boost converter 2 is enabled as soon as VGL has finished ramping down. To minimize inrush current during start-up, boost converter 2 ramps VGH linearly to its programmed value in tSS4 seconds. Soft-start time tSS4 can be programmed from 0.256 ms to 35 ms using the SS4 register. Because boost converter 2 is non-synchronous, its output is already equal to AVDD (minus the voltage drop across its rectifier diode) before it starts switching, which means that the time during which VGH is actually ramping during start-up is less than the actual programmed soft-start time (see Figure 5-5).

TPS65154 G505_SLVSBG2.gif Figure 5-5 Boost Converter 2 Soft-Start

5.3.3.2 Power-Down (Boost Converter 2)

Boost converter 2 is disabled when VIN<VUVLO. The converter's output is not actively discharged when the converter is disabled.

5.3.3.3 Protection (Boost Converter 2)

Boost converter 2 is protected against short-circuits and undervoltage conditions. An undervoltage condition is detected if the boost converter's output falls below 70% of its programmed voltage for longer than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the boost converter's output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-circuit detection has no time delay associated with it). To recover normal operation following either an undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR applied.

5.3.4 Negative Charge Pump (VGL)

The negative charge pump inverts AVDD and regulates its output to the voltage set by the VGL register. VGL can be programmed from –5 V to –8 V in 0.2 V steps using the VGL register, however, since the negative charge pump inverts AVDD to generate its output, the most negative voltage that can be generated is approximately –AVDD+1 V. Thus, if AVDD = 8.0 V, the usable range of VGL is approximately –5 V to –7 V. If VGL is programmed to a more negative voltage than this the charge pump may not be able to regulate its output. This will not damage the IC, but performance may be impaired.

The negative charge pump in the TPS65154 is fully integrated and requires only two external capacitors to operate (a flying capacitor connected between the C1A and C1B pins, and an output capacitor connected between the VGL pin and ground).

TPS65154 G506_SLVSBG2.gif Figure 5-6 Negative Charge Pump Block Diagram

5.3.4.1 Power-Up (Negative Charge Pump)

The negative charge pump starts tDLY3 milliseconds after boost converter 1 (AVDD) starts ramping and ramps its output linearly from zero to its programmed output voltage in tSS3 ms. Delay time tDLY3 can be programmed from 0 ms to 35 ms using the DLY3 register. Soft-start time tSS3 can be programmed from 0 ms to 35 ms using the SS3 register.

5.3.4.2 Power-Down (Negative Charge Pump)

The negative charge pump is disabled when the supply voltage falls below the undervoltage lockout threshold (VIN<VUVLO). During power-down the charge pump's output is actively discharge to GND.

5.3.4.3 Protection (Negative Charge Pump)

The negative charge pump is protected against short-circuits and undervoltage conditions. An undervoltage condition is detected if the charge pump's output falls below 70% of its programmed voltage for longer than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the charge pump's output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-circuit detection has no time delay associated with it). To recover normal operation following either an undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR applied.

5.3.5 Gate Voltage Shaping

The gate voltage shaping function can be used to reduce image sticking in LCD panels by modulating the LCD panel's gate ON voltage (VGH). Figure 5-7 shows a block diagram of the gate voltage shaping function and Figure 5-8 shows the typical waveforms during operation.

TPS65154 G507_SLVSBG2.gif Figure 5-7 Gate Voltage Shaping Block Diagram
TPS65154 G508_SLVSBG2.gif Figure 5-8 Gate Voltage Shaping Waveforms

Gate voltage shaping is controlled by the FLK input. When FLK is high, Q1 is on, Q2, Q3 and Q4 are off, and VGHM is equal to VGH. On the falling edge of FLK, Q1 is turned off, Q2 and Q3 are turned on, and the LCD panel load connected to the VGHM pin discharges through the external resistor connected to the RE pin.

During power-up, Q1, Q2 and Q3 are held off and Q4 is turned on, pulling the VGHM pin pulled to GND, regardless of the state of the FLK signal, until tDLY4 milliseconds after boost converter 2 (VGH) has finished ramping. The value of tDLY4 can be programmed from 0 ms to 35 ms using the DLY4 register.

During power-down Q1 is held permanently on and Q2, Q3 and Q4 permanently off, regardless of the state of the FLK signal.

5.3.6 Panel Discharge (XAO)

The TPS65154 provides an output signal via its XAO pin that can be used to drive the outputs of the display panel's gate driver IC high during power-down. The XAO pin is pulled low whenever VIN<VDET. The VDET threshold voltage can be configured using the VDET register.

The XAO output is an open-drain type and requires an external pull-up, typically in the range 10 kΩ to 100 kΩ.

5.3.7 Reset Generator (RST)

The RST pin generates an active-low reset signal for the rest of the system. During power-up, the reset timer starts when VCC has finished ramping. The reset pulse duration tRST can be programmed from 0 ms to 15 ms using the RESET register. The RST signal is latched when it goes high and will not be taken low again until the device is powered down (even if VCC temporarily falls out of regulation). The active power-down threshold (VUVLO or VDET) can be selected using the RMODE bit in the CONFIG register.

The RST output is an open-drain type that requires an external pull-up resistor. Pull-up resistor values in the range 10 kΩ to 100 kΩ are recommended for most applications.

5.3.8 Programmable VCOM

The programmable VCOM uses three digital-to-analog converters (DACs) to generate a VCOM voltage that is subsequently buffered by a high-speed op-amp. The maximum value of VCOM is set by the 4-bit VMAX register, and can be programmed in the range 2.5/8×AVDD to 4/8×AVDD. The minimum value of VCOM is set by the 4-bit VMIN register, and can be programmed in the range 2/8 × AVDD to 3.5/8 × AVDD. Note, for proper operation, VMAX must be greater than VMIN. By programming the 7-bit VCOM parameter, users can adjust the VCOM voltage appearing at the OUT pin between VMIN and VMAX as follows:

Equation 1. TPS65154 VCOM_equation.gif

where VCOM is the value stored in the Wiper Register (see Figure 5-9).

TPS65154 G509_SLVSBG2.gif Figure 5-9 Programmable VCOM Block Diagram

The programmable VCOM function has three registers. The volatile Wiper Register (WR) contains the value currently output by the programmable VCOM DAC; this value is lost when power to the device is removed. The non-volatile Initial Value Register (IVR) contains the value loaded into the DAC every time the device is powered up. The Control Register (CR) determines whether data is written to or read from the WR, the IVR, or both. If the CR contains 00h, during write operations data is stored in the WR and the IVR, and during read operations data is read from the IVR. If the CR contains 80h, data is written to and read from the WR register only. 00h and 80h are the only valid values for the CR. Table 5-1 shows the programmable VCOM's register address map.

Table 5-1 Programmable VCOM Register Address Map

REGISTER ADDRESS NON-VOLATILE VOLATILE
00h Initial Value Register (IVR) Wiper Register (WR)
02h Not Used Control Register (CR)

5.3.8.1 Operational Amplifier Performance

Like most op-amps, the VCOM op-amp in the TPS65154 is not designed to drive purely capacitive loads, so it is not recommended to connect a capacitor directly to its output in an attempt to increase performance; however, the op-amp is capable of delivering high peak currents that make such capacitors unnecessary in most applications.

High-speed op amps such as the one in the TPS65154 require care when using them. The most common problem is when parasitic capacitance at the inverting input creates a pole with the feedback resistor, reducing amplifier stability. Two things can be done to minimize the likelihood of this happening. Both of these work by shifting the pole (which can never be completely eliminated) to a frequency outside the op amp's bandwidth, where it has no effect.

  • Reduce the value of the feedback resistor. In applications where no feedback from the panel is used, the feedback resistor can be made zero. In applications where a non-zero feedback resistor has to be used, a small capacitor (between 10 pF and 100 pF) across the feedback resistor will minimize ringing.
  • Minimize the parasitic capacitance at the op amp's inverting input. This is achieved by using short PCB traces between the feedback resistor and the inverting input, and by removing ground planes and other copper areas above and below this PCB trace.

5.3.8.2 Power-Up (Programmable VCOM)

The programmable VCOM is enabled when AVDD > VUVLO2.

5.3.8.3 Power-Down (Programmable VCOM)

During power-down, the programmable VCOM continues to operate until AVDD < VUVLO2.

5.3.9 WLED Driver

5.3.9.1 WLED Boost Converter

The WLED boost converter boosts a 4.5 V to 24 V supply VBAT to a higher voltage to supply the LED strings connected to the WLED driver. It uses a fixed-frequency, current-mode topology. The converter's output voltage is automatically adjusted to maintain the lowest feedback voltage (IFB1 to IFB6) between 450 mV and 750 mV, thus ensuring sufficient headroom for the output current sinks, but without dissipating excessive power in the IC. This approach automatically compensates for changes in the LED string voltage, for example, because of temperature effects. The WLED boost converter's switching frequency can be programmed to 400 kHz, 600 kHz, 800 kHz, and 1 MHz using the FSW3 register.

The WLED boost converter features a soft-start circuit to limit inrush current when the converter starts. The duration of the soft-start ramp depends on the value of the capacitor connected to the COMP3 pin. Note, that because the converter is a non-synchronous type, its output voltage before it starts switching is equal to VBAT (minus the voltage drop across its rectifier).

5.3.9.2 Current Sinks

The brightness of the LED strings is determined by the average current flowing through each string, which is the product of the output duty cycle and the current sink's output current. The output current of all current sinks is the same and is set by the external resistor connected between the ISET pin and ground:

Equation 2. TPS65154 wled_iset_equation_lvsbg2.gif

where:

  • VSET is the voltage on the ISET pin
  • RSET is the resistance between the ISET pin and GND
  • KSET is a constant

When the TPS65154 measures zero current flowing in one of the IFB pins it determines that the string is open and automatically disables that output. The WLED boost converter's output voltage is subsequently regulated according to the remaining operational strings. If an application uses fewer than six LED strings, it is recommended to connected the unused outputs to ground; this ensures the most rapid detection of the unused strings. Once open strings have been detected, they remain disabled until a POR occurs or EN is toggled.

5.3.9.3 Protection

The WLED boost converter and dimming circuits feature a variety of protection schemes to ensure reliable operation when subjected to various failure modes. These protection schemes are listed in Table 5-2.

Table 5-2 WLED Driver Protection

ERROR DETECTION ACTION RECOVERY
WLED boost converter output voltage too high VOVP exceeds programmed threshold
(30 V, 33 V, 36 V or 39 V)		 WLED boost converter output regulated to programmed threshold None required
WLED boost converter switch current too high ISW > ILIM Switch turned off Switch automatically re-enabled at start of next switching cycle
All LED strings open-circuit IIFB = 0 mA and VOUT = VOVP Disable all output channels and boost converter Output channels re-enabled following power cycle
Individual LED string(s) open-circuit IIFB = 0 mA and VOUT = VOVP Disable affected output channel(s)
Functional output channels continue operating.		 Affected output channel(s) re-enabled following power cycle
Individual LED string(s) shorted-circuited to ground IIFB = 0 mA for longer than 4 ms

5.3.9.4 Enable and Start-Up

The WLED driver is enabled and disabled by EN, however, this signal has no effect until the LCD bias functions have completed their start-up sequence. Following a POR, EN has no effect until tDLY4 is complete; after that the WLED driver can be enabled and disabled at any time using EN (providing nothing happens to cause the LCD bias functions to re-start) and applying a PWM signal. In applications that do not generate an EN signal, the EN pin can be tied to VIN, in which case the WLED driver will start automatically at the end of tDLY4. Note, that a permanently low PWM signal (0% duty cycle) will prevent boost converter 3 from starting-up.

When the WLED driver is enabled it first checks the status of IFB1 to IFB6 and shuts down any channels that it detects are disabled/unused. These channels will be subsequently ignored until a POR occurs or EN is toggled.

5.3.10 Undervoltage Lockout

An undervoltage lockout function disables the IC when the supply voltage is too low for proper operation.

5.4 Device Functional Modes

5.4.1 Dimming Modes

The TPS65154 support direct dimming and phase-shift dimming modes. The active dimming mode can be selected using the DMODE bit in the CONFIG register.

5.4.1.1 Direct Dimming

When direct dimming is selected, the output current sinks are controlled directly by the PWM signal. In this mode, they are turned on and off together, at the same frequency and duty cycle as the PWM signal (see Figure 5-10).

TPS65154 G510_SLVSBG2.gif Figure 5-10 Direct Dimming

5.4.1.2 Phase-Shift Dimming

When phase-shift dimming mode is selected, the output dimming frequency does not depend on the frequency of the PWM signal but can be independently programmed from 15 kHz to 22 kHz using the FDIM register. In this mode, the duty cycle information contained in the PWM signal is extracted and re-used to generate up to six outputs, at the output frequency set by the FDIM register, and phase-shifted with respect to each other by 360°/N, where N is the number of outputs in use (see Figure 5-11). Using phase-shifted outputs, the maximum load current step is reduced by the same factor N, resulting in reduced voltage ripple on the boost converter's output and consequently lower audible noise.

TPS65154 G511_SLVSBG2.gif Figure 5-11 Phase-Shift Dimming

5.4.2 Power Sequencing

Figure 5-12 shows the typical power-up/down characteristic of the TPS65154.

5.4.2.1 Power-Up

VCC starts ramping tDLY1 seconds after VIN > VUVLO.

RST is initially held low. tRST seconds after VCC has finished ramping RST goes high.

AVDD starts ramping tDLY2 seconds after RST has gone high.

VGL starts ramping tDLY3 seconds after AVDD starts ramping.

VGH starts ramping as soon as VGL has finished ramping.

VGHM is initially held low (connected to RE). tDLY4 seconds after VGH has finished ramping, gate voltage shaping is enabled and VGHM follows the state of FLK.

XAO is initially held low. tDLY6 seconds after VIN>VDET XAO goes high.

The WLED driver is enabled by the logical AND of AVDD (that is, AVDD has finished ramping) and EN.

5.4.2.2 Power-Down

VCC, AVDD, VGH and VGL are disabled when VIN<VUVLO.

XAO goes low when VIN falls below the threshold selected for it (VUVLO or VDET).

RST goes low when VIN falls below the threshold selected for it (VUVLO or VDET).

The WLED driver is turned off when EN = 0 or VIN < VUVLO.

TPS65154 G548_SLVSBG2.gif Figure 5-12 Power Up/Down Sequencing

5.5 Programming

5.5.1 Configuration

The TPS65154 divides the configuration parameters into two categories:

  • Configuration parameters
  • VCOM

In typical applications, all configuration parameters except VCOM are programmed by the subcontractor during PCB assembly, and VCOM is programmed by the display manufacturer during display calibration.

5.5.1.1 General

Configuration parameters can be changed by writing the desired values to the appropriate RAM register(s). The RAM registers are volatile and their contents are lost when power is removed from the device. By writing to the Control Register, it is possible to store the active configuration in non-volatile EEPROM; during power-up, the contents of the EEPROM are copied into the RAM registers and used to configure the device.

5.5.1.1.1 I2C Interface

The TPS65154 features an industry-standard I2C interface that supports both Standard and Fast modes of operation.

5.5.1.1.2 Slave Addresses

The configuration parameters are all accessed using slave address 74h and the VCOM is accessed using slave address 28h.

5.5.1.1.3 Write Protect

An active-high Write Protect pin (WP) prevents the configuration parameters from being changed by accident. This pin is internally pulled high and must be actively pulled low to access to the EEPROM or RAM registers. Note that the WP pin disables all I2C traffic to the TPS65154, and must also be pulled low during read operations. This is to ensure that noise present on the I2C lines does not erroneously overwrite the active configuration stored in RAM (which would not be protected by a simple EEPROM write-protect scheme). The write protect function can be enabled and disabled using the WPEN bit in the CONFIG register. Note that once the write protect function is enabled it is not possible to disable again it without pulling the WP pin low. For this reason, it is strongly recommended that applications include some way to pull the WP pin low (for example, a test pad), even if it is not normally used.

5.5.2 Programming Examples (Excluding VCOM)

5.5.2.1 Writing to a Single RAM Register

  1. Bus master sends START condition
  2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  3. TPS65154 acknowledges
  4. Bus master sends address of RAM register (00h)
  5. TPS65154 acknowledges
  6. Bus master sends data to be written
  7. TPS65154 acknowledges
  8. Bus master sends STOP condition
TPS65154 G535_SLVSBG2.gif Figure 5-13 Writing to a Single RAM Register

5.5.2.2 Writing to Multiple RAM Registers

  1. Bus master sends START condition
  2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
  3. TPS65154 acknowledges
  4. Bus master sends address of first RAM register to be written to (00h)
  5. TPS65154 acknowledges
  6. Bus master sends data to be written to first RAM register
  7. TPS65154 acknowledges
  8. Bus master sends data to be written to RAM register at next higher address (auto-increment)
  9. TPS65154 acknowledges
  10. Steps (8) and (9) repeated until data for final RAM register has been sent
  11. TPS65154 acknowledges
  12. Bus master sends STOP condition
TPS65154 G536_SLVSBG2.gif Figure 5-14 Writing to Multiple RAM Registers

5.5.2.3 Saving Contents of all RAM Registers to EEPROM

  1. Bus master sends START condition
  2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  3. TPS65154 acknowledges
  4. Bus master sends address of Control Register (FFh)
  5. TPS65154 acknowledges
  6. Bus master sends data to be written to the Control Register (80h)
  7. TPS65154 acknowledges
  8. Bus master sends STOP condition
TPS65154 G537_SLVSBG2.gif Figure 5-15 Saving Contents of all RAM Registers to EEPROM

5.5.2.4 Reading from a Single RAM Register

  1. Bus master sends START condition
  2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  3. TPS65154 acknowledges
  4. Bus master sends address of Control Register (FFh)
  5. TPS65154 acknowledges
  6. Bus master sends data for Control Register (00h)
  7. TPS65154 acknowledges
  8. Bus master sends STOP condition
  9. Bus master sends START condition
  10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  11. TPS65154 acknowledges
  12. Bus master sends address of RAM register (00h)
  13. TPS65154 acknowledges
  14. Bus master sends REPEATED START condition
  15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
  16. TPS65154 acknowledges
  17. TPS65154 sends RAM register data
  18. Bus master does not acknowledge
  19. Bus master sends STOP condition
TPS65154 G538_SLVSBG2.gif Figure 5-16 Reading from a Single RAM Register

5.5.2.5 Reading from a Single EEPROM Register

  1. Bus master sends START condition
  2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  3. TPS65154 acknowledges
  4. Bus master sends address of Control Register (FFh)
  5. TPS65154 acknowledges
  6. Bus master sends data for Control Register (01h)
  7. TPS65154 acknowledges
  8. Bus master sends STOP condition
  9. Bus master sends START condition
  10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  11. TPS65154 acknowledges
  12. Bus master sends address of EEPROM register (00h)
  13. TPS65154 acknowledges
  14. Bus master sends REPEATED START condition
  15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
  16. TPS65154 acknowledges
  17. TPS65154 sends EEPROM register data
  18. Bus master does not acknowledge
  19. Bus master sends STOP condition
TPS65154 G539_SLVSBG2.gif Figure 5-17 Reading from a Single EEPROM Register

5.5.2.6 Reading from Multiple RAM Registers

  1. Bus master sends START condition
  2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  3. TPS65154 acknowledges
  4. Bus master sends address of Control Register (FFh)
  5. TPS65154 acknowledges
  6. Bus master sends data for Control Register (00h)
  7. TPS65154 acknowledges
  8. Bus master sends STOP condition
  9. Bus master sends START condition
  10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  11. TPS65154 acknowledges
  12. Bus master sends address of first register to be read (00h)
  13. TPS65154 acknowledges
  14. Bus master sends REPEATED START condition
  15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
  16. TPS65154 acknowledges
  17. TPS65154 sends contents of first RAM register to be read
  18. Bus master acknowledges
  19. TPS65154 sends contents of second RAM register to be read
  20. Bus master acknowledges
  21. TPS65154 sends contents of third (last) RAM register to be read
  22. Bus master does not acknowledge
  23. Bus master sends STOP condition
TPS65154 G540_SLVSBG2.gif Figure 5-18 Reading from Multiple RAM Registers

5.5.2.7 Reading from Multiple EEPROM Registers

  1. Bus master sends START condition
  2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  3. TPS65154 acknowledges
  4. Bus master sends address of Control Register (FFh)
  5. TPS65154 acknowledges
  6. Bus master sends data for Control Register (01h)
  7. TPS65154 acknowledges
  8. Bus master sends STOP condition
  9. Bus master sends START condition
  10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
  11. TPS65154 acknowledges
  12. Bus master sends address of first EEPROM register to be read (00h)
  13. TPS65154 acknowledges
  14. Bus master sends REPEATED START condition
  15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
  16. TPS65154 acknowledges
  17. TPS65154 sends contents of first EEPROM register to be read
  18. Bus master acknowledges
  19. TPS65154 sends contents of second EEPROM register to be read
  20. Bus master acknowledges
  21. TPS65154 sends contents of third (last) EEPROM register to be read
  22. Bus master does not acknowledge
  23. Bus master sends STOP condition
TPS65154 G541_SLVSBG2.gif Figure 5-19 Reading from Multiple EEPROM Registers

5.5.3 Programming Examples - VCOM

5.5.3.1 Writing a VCOM Value of 77h to WR

  1. The bus master sends a START condition.
  2. The bus master sends 7-bit slave address plus low R/W bit.
  3. TPS65154 slave acknowledges.
  4. The bus master sends the CR address of 02h.
  5. The TPS65154 acknowledges.
  6. The bus master sends the CR contents of 80h.
  7. The TPS65154 slave acknowledges.
  8. The bus master sends a STOP condition.
  9. The bus master sends a START condition.
  10. The bus master sends 7-bit slave address plus low R/W bit.
  11. TPS65154 slave acknowledges.
  12. The bus master sends the WR address of 00h.
  13. The TPS65154 acknowledges.
  14. The bus master sends the WR contents of 77h (right-justified).
  15. The TPS65154 slave acknowledges.
  16. The bus master sends a STOP condition.
TPS65154 G544_SLVSBG2.gif Figure 5-20 Writing a VCOM Value of 77h to WR

5.5.3.2 Writing a VCOM Value of 77h to IVR and WR

  1. The bus master sends a START condition.
  2. The bus master sends 7-bit slave address plus low R/W bit.
  3. TPS65154 slave acknowledges.
  4. The bus master sends the CR address of 02h.
  5. The TPS65154 acknowledges.
  6. The bus master sends the CR contents of 00h.
  7. The TPS65154 slave acknowledges.
  8. The bus master sends a STOP condition.
  9. The bus master sends a START condition.
  10. The bus master sends 7-bit slave address plus low R/W bit.
  11. TPS65154 slave acknowledges.
  12. The bus master sends the WR address of 00h.
  13. The TPS65154 acknowledges.
  14. The bus master sends the WR contents of 77h (right-justified).
  15. The TPS65154 slave acknowledges.
  16. The bus master sends a STOP condition.
TPS65154 G545_SLVSBG2.gif Figure 5-21 Writing a VCOM Value of 77h to IVR and WR

5.5.3.3 Reading a VCOM Value of 77h from WR

  1. The bus master sends a START condition.
  2. The bus master sends 7-bit slave address plus low R/W bit.
  3. TPS65154 slave acknowledges.
  4. The bus master sends the CR address of 02h.
  5. The TPS65154 acknowledges.
  6. The bus master sends the CR contents of 80h.
  7. The TPS65154 slave acknowledges.
  8. The bus master sends a STOP condition.
  9. The bus master sends a START condition.
  10. The bus master sends 7-bit slave address plus low R/W bit.
  11. TPS65154 slave acknowledges.
  12. The bus master sends the WR address of 00h.
  13. The TPS65154 acknowledges.
  14. The bus master sends a REPEATED START condition.
  15. The bus master sends 7-bit slave address plus high R/W bit.
  16. The TPS65154 sends the WR contents of 77h (right-justified).
  17. The bus master does not acknowledge.
  18. The bus master sends a STOP condition.
TPS65154 G546_SLVSBG2.gif Figure 5-22 Reading 77h from WR

5.5.3.4 Reading a VCOM Value of 77h from IVR

  1. The bus master sends a START condition.
  2. The bus master sends 7-bit slave address plus low R/W bit.
  3. TPS65154 slave acknowledges.
  4. The bus master sends the CR address of 02h.
  5. The TPS65154 acknowledges.
  6. The bus master sends the CR contents of 00h.
  7. The TPS65154 slave acknowledges.
  8. The bus master sends a STOP condition.
  9. The bus master sends a START condition.
  10. The bus master sends 7-bit slave address plus low R/W bit.
  11. TPS65154 slave acknowledges.
  12. The bus master sends the WR address of 00h.
  13. The TPS65154 acknowledges.
  14. The bus master sends a REPEATED START condition.
  15. The bus master sends 7-bit slave address plus high R/W bit.
  16. The TPS65154 sends the WR contents of 77h (right-justified).
  17. The bus master does not acknowledge.
  18. The bus master sends a STOP condition.
TPS65154 G547_SLVSBG2.gif Figure 5-23 Reading 77h from IVR

5.6 Register Map

5.6.1 Configuration Registers (Excluding VCOM)

Table 5-3 shows the memory map of the configuration parameters.

Table 5-3 Configuration Memory Map

REGISTER ADDRESS REGISTER NAME FACTORY DEFAULT DESCRIPTION
00h CONFIG 02h KMODE = 0
WPEN = 0
DMODE = 1
RMODE = 0		 Sets miscellaneous configuration bits
01h VCC 03h 2.5 V Sets the output voltage of the linear regulator (VCC)
02h DLY1 02h 10 ms Sets the start-up delay of the linear regulator (VCC)
03h AVDD 0Fh 8.0 V Sets the output voltage of boost converter 1 (AVDD)
04h FSW1 01h 600 kHz Sets the switching frequency of boost converter 1 (AVDD)
05h SS2 04h 20 ms Sets the soft-start time of boost converter 1 (AVDD)
06h DLY2 02h 10 ms Sets the start-up delay of boost converter 1 (AVDD)
07h VGL 09h –6.8 V Sets the output voltage of the negative charge pump (VGL)
08h SS3 01h 5 ms Sets the soft-start time of the negative charge pump (VGL)
09h DLY3 01h 5 ms Sets the start-up delay of the negative charge pump (VGL)
0Ah VGH 04h 20.0 V Sets the output voltage of boost converter 2 (VGH)
0Bh SS4 01h 5 ms Sets the soft-start time of boost converter 2 (VGH)
0Ch FSW3 01h 600 kHz Sets the switching frequency of boost converter 3 (WLED)
0Dh DLY4 02h 10 ms Sets the start-up delay of the gate voltage shaping function (VGHM)
0Eh OVP 03h 39 V Sets the over-voltage protection threshold of boost converter 3 (WLED)
0Fh FDIM 07h 22 kHz Sets the output dimming frequency of the WLED driver in phase-shift dimming mode
10h RESET 05h 5 ms Sets the reset pulse duration
11h VDET 00h VDET = VUVLO Sets the threshold of the RST and XAO signals
12h DLY6 02h 30 ms Sets the start-up delay of the XAO signal
13h VMAX 07h 3.2 V Sets the maximum VCOM voltage
14h VMIN 07h 2.7 V Sets the minimum VCOM voltage
15h USER1 00h 00h For customer use
FFh CONTROL 00h Controls whether read and write operations access RAM or EEPROM registers

5.6.1.1 CONFIG (00h)

The CONFIG register can be written to and read from.

Figure 5-24 CONFIG Register Bit Allocation
7 6 5 4 3 2 1 0
ADIS Reserved KMODE WPEN DMODE RMODE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-4 CONFIG Register Field Descriptions

Bit Field Value Description
7 ADIS This bit can be used to disable boost converter 1 (AVDD), boost converter 2 (VGH) and the negative charge pump (VGL) during device programming. This bit is volatile and is never stored in EEPROM. It is always reset (that is, ADIS = 0) following power-up, that is, the affected converters are always enabled following power-up.
0 Boost converter 1 (AVDD), boost converter 2 (VGH), and negative charge pump (VGL) enabled.
1 Boost converter 1 (AVDD), boost converter 2 (VGH), and negative charge pump (VGL) disabled.
6-4 Reserved N/A These bits are reserved for future use and should be programmed to 0 to ensure proper operation.
3 KMODE This bit can be used to enable and disable boost converter 1's active discharge function.
0 Boost converter 1 (AVDD) active discharge enabled.
1 Boost converter 1 (AVDD) active discharge disabled.
2 WPEN This bit can be used to enable and disable the write protect function.
0 Disabled. WP not used and I2C interface always active.
1 Enabled. I2C interface only active when WP pulled low.
1 DMODE This bit determines which dimming mode is used by the WLED driver.
0 Direct dimming.
1 Phase-shift dimming.
0 RMODE This bit determines which threshold is used to assert RST during power-down.
0 VUVLO threshold used.
1 VDET threshold used.

5.6.1.2 VCC (01h)

The VCC register can be written to and read from.

Figure 5-25 VCC Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented VCC
R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-5 VCC Register Field Descriptions

Bit Field Value Description
7-2 Not implemented N/A These bits are not implemented. During write operations, data for these bits is ignored, and during read operations 0 is returned.
1-0 VCC These bits determine the output voltage of the linear regulator (VCC).
0h 1.0 V
1h 1.2 V
2h 1.89 V
3h 2.5 V

5.6.1.3 DLY1 (02h)

The DLY1 register can be written to and read from.

Figure 5-26 DLY1 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented DLY1
R/W-0 R/W-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-6 DLY1 Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during write operations 0 is returned.
3-0 DLY1 These bits determine how soon after VIN>VUVLO the linear regulator (VCC) starts.
0h 0 ms
1h 5 ms
2h 10 ms
3h 15 ms
4h 20 ms
5h 25 ms
6h 30 ms
7h 35 ms
8h 40 ms
9h 45 ms
Ah 50 ms
Bh 55 ms
Ch 60 ms
Dh 65 ms
Eh 70 ms
Fh 75 ms

5.6.1.4 AVDD (03h)

The AVDD register can be written to and read from.

Figure 5-27 AVDD Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented AVDD
R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-7 AVDD Register Field Descriptions

Bit Field Value Description
1 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
0 AVDD These bits determine the output voltage of boost converter 1 (AVDD).
00h 6.5 V
01h 6.6 V
02h 6.7 V
03h 6.8 V
04h 6.9 V
05h 7.0 V
06h 7.1 V
07h 7.2 V
08h 7.3 V
09h 7.4 V
0Ah 7.5 V
0Bh 7.6 V
0Ch 7.7 V
0Dh 7.8 V
0Eh 7.9 V
0Fh 8.0 V
10h 8.1 V
11h 8.2 V
12h 8.3 V
13h 8.4 V
14h 8.5 V
15h 8.6 V
16h 8.7 V
17h 8.8 V
18h 8.9 V
19h 9.0 V
1Ah 9.1 V
1Bh 9.2 V
1Ch 9.3 V
1Dh 9.4 V
1Eh 9.5 V
1Fh 9.6 V

5.6.1.5 FSW1 (04h)

The FSW1 register can be written to and read from.

Figure 5-28 FSW1 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented FSW1
R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-8 FSW1 Register Field Descriptions

Bit Field Value Description
7-2 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
1-0 FSW1 These bits determine the switching frequency of boost converter 1 (AVDD).
0h 400 kHz
1h 600 kHz
2h 800 kHz
3h 1 MHz

5.6.1.6 SS2 (05h)

The SS2 register can be written to and read from.

Figure 5-29 SS2 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented SS2
R/W-0 R/W-1 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-9 SS2 Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 SS2 These bits determine the soft-start time of boost converter 1 (AVDD).
0h 0.5 ms
1h 5 ms
2h 10 ms
3h 15 ms
4h 20 ms
5h 25 ms
6h 30 ms
7h 35 ms
8h 40 ms
9h 45 ms
Ah 50 ms
Bh 55 ms
Ch 60 ms
Dh 65 ms
Eh 70 ms
Fh 75 ms

5.6.1.7 DLY2 (06h)

The DLY2 register can be written to and read from.

Figure 5-30 DLY2 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented DLY2
R/W-0 R/W-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-10 DLY2 Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 DLY2 These bits determine how soon after RST goes high boost converter 1 (AVDD) starts.
0h 0 ms
1h 5 ms
2h 10 ms
3h 15 ms
4h 20 ms
5h 25 ms
6h 30 ms
7h 35 ms
8h 40 ms
9h 45 ms
Ah 50 ms
Bh 55 ms
Ch 60 ms
Dh 65 ms
Eh 70 ms
Fh 75 ms

5.6.1.8 VGL (07h)

The VGL register can be written to and read from.

Figure 5-31 VGL Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented VGL
R/W-1 R/W-0 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-11 VGL Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 VGL These bits determine the output voltage of the negative charge pump (VGL).
0h –5.0 V
1h –5.2 V
2h –5.4 V
3h –5.6 V
4h –5.8 V
5h –6.0 V
6h –6.2 V
7h –6.4 V
8h –6.6 V
9h –6.8 V
Ah –7.0 V
Bh –7.2 V
Ch –7.4 V
Dh –7.6 V
Eh –7.8 V
Fh –8.0 V

5.6.1.9 SS3 (08h)

The SS3 register can be written to and read from.

Figure 5-32 SS3 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented SS3
R/W-0 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-12 SS3 Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 SS3 These bits determine the soft-start time of the negative charge pump (VGL).
0h 0.256 ms
1h 5 ms
2h 10 ms
3h 15 ms
4h 20 ms
5h 25 ms
6h 30 ms
7h 35 ms

5.6.1.10 DLY3 (09h)

The DLY3 register can be written to and read from.

Figure 5-33 DLY3 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented DLY3
R/W-0 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-13 DLY3 Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 DLY3 These bits determine how soon after boost converter 1 (AVDD) starts the negative charge pump (VGL) starts.
0h 0 ms
1h 5 ms
2h 10 ms
3h 15 ms
4h 20 ms
5h 25 ms
6h 30 ms
7h 35 ms

5.6.1.11 VGH (0Ah)

The VGH register can be written to and read from.

Figure 5-34 VGH Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented VGH
R/W-0 R/W-1 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-14 VGH Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 VGH These bits determine the output voltage of boost converter 2 (VGH).
0h 18.0 V
1h 18.5 V
2h 19.0 V
3h 19.5 V
4h 20.0 V
5h 20.5 V
6h 21.0 V
7h 21.5 V
8h 22 0 V
9h 22.5 V
Ah 23.0 V
Bh 23.5 V
Ch 24.0 V
Dh 24.5 V
Eh 25.0 V
Fh 25.5 V

5.6.1.12 SS4 (0Bh)

The SS4 register can be written to and read from.

Figure 5-35 SS4 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented SS4
R/W-0 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-15 SS4 Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 SS4 These bits determine the soft-start time of boost converter 2 (VGH).
0h 0.256 ms
1h 5 ms
2h 10 ms
3h 15 ms
4h 20 ms
5h 25 ms
6h 30 ms
7h 35 ms

5.6.1.13 FSW3 (0Ch)

The FSW3 register can be written to and read from.

Figure 5-36 FSW3 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented FSW3
R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-16 FSW3 Register Field Descriptions

Bit Field Value Description
7-2 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
1-0 FSW3 These bits determine the switching frequency of boost converter 3 (WLED).
0h 400 kHz
1h 600 kHz
2h 800 kHz
3h 1 MHz

5.6.1.14 DLY4 (0Dh)

The DLY4 register can be written to and read from.

Figure 5-37 DLY4 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented DLY4
R/W-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-17 DLY4 Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 DLY4 These bits determine the start-up delay of the gate voltage shaping function.
0h 0 ms
1h 5 ms
2h 10 ms
3h 15 ms
4h 20 ms
5h 25 ms
6h 30 ms
7h 35 ms

5.6.1.15 OVP (0Eh)

The OVP register can be written to and read from.

Figure 5-38 OVP Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented OVP
R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-18 OVP Register Field Descriptions

Bit Field Value Description
7-2 Not implemented N/A These bits are not implemented. During write operations, data for these bits is ignored, and during read operations 0 is returned.
1-0 OVP These bits determine the overvoltage threshold of boost converter 3 (WLED).
0h 30 V
1h 33 V
2h 36 V
3h 39 V

5.6.1.16 FDIM (OFh)

The FDIM register can be written to and read from.

Figure 5-39 FDIM Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented FDIM
R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-19 FDIM Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 FDIM These bits determine the WLED driver's output dimming frequency in phase-shift dimming mode.
0h 15 kHz
1h 16 kHz
2h 17 kHz
3h 18 kHz
4h 19 kHz
5h 20 kHz
6h 21 kHz
7h 22 kHz

5.6.1.17 RESET (10h)

The RESET register can be written to and read from.

Figure 5-40 RESET Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented RESET
R/W-0 R/W-1 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-20 RESET Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 RESET These bits determine the duration of the reset pulse (RST).
0h 0 ms
1h 1 ms
2h 2 ms
3h 3 ms
4h 4 ms
5h 5 ms
6h 6 ms
7h 7 ms
8h 8 ms
9h 9 ms
Ah 10 ms
Bh 11 ms
Ch 12 ms
Dh 13 ms
Eh 14 ms
Fh 15 ms

5.6.1.18 VDET (11h)

The VDET register can be written to and read from.

Figure 5-41 VDET Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented VDET
R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-21 VDET Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 VDET These bits determine the threshold voltage of the XAO signal.
0h VUVLO
1h 2.0 V
2h 2.1 V
3h 2.2 V
4h 2.3 V
5h 2.4 V
6h 2.5 V
7h 2.6 V
8h 2.7 V
9h 2.8 V
Ah 2.9 V
Bh 3.0 V
Ch 3.0 V
Dh 3.0 V
Eh 3.0 V
Fh 3.0 V

5.6.1.19 DLY6 (12h)

The DLY6 register can be written to and read from.

Figure 5-42 DLY6 Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented DLY6
R/W-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-22 DLY6 Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 DLY6 These bits determine the start-up delay time of the XAO signal.
0h 0 ms
1h 5 ms
2h 10 ms
3h 15 ms
4h 20 ms
5h 25 ms
6h 30 ms
7h 35 ms

5.6.1.20 VMAX (13h)

The VMAX register can be written to and read from.

Figure 5-43 VMAX Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented VMAX
R/W-0 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-23 VMAX Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 VMAX These bits determine the maximum VCOM voltage.
0h 2.5/8 × AVDD
1h 2.6/8 × AVDD
2h 2.7/8 × AVDD
3h 2.8/8 × AVDD
4h 2.9/8 × AVDD
5h 3.0/8 × AVDD
6h 3.1/8 × AVDD
7h 3.2/8 × AVDD
8h 3.3/8 × AVDD
9h 3.4/8 × AVDD
Ah 3.5/8 × AVDD
Bh 3.6/8 × AVDD
Ch 3.7/8 × AVDD
Dh 3.8/8 × AVDD
Eh 3.9/8 × AVDD
Fh 4.0/8 × AVDD

5.6.1.21 VMIN (14h)

The VMIN register can be written to and read from.

Figure 5-44 VMIN Register Bit Allocation
7 6 5 4 3 2 1 0
Not Implemented VMIN
R/W-0 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-24 VMIN Register Field Descriptions

Bit Field Value Description
7-4 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0 VMIN These bits determine the minimum VCOM voltage.
0h 2.0/8 × AVDD
1h 2.1/8 × AVDD
2h 2.2/8 × AVDD
3h 2.3/8 × AVDD
4h 2.4/8 × AVDD
5h 2.5/8 × AVDD
6h 2.6/8 × AVDD
7h 2.7/8 × AVDD
8h 2.8/8 × AVDD
9h 2.9/8 × AVDD
Ah 3.0/8 × AVDD
Bh 3.1/8 × AVDD
Ch 3.2/8 × AVDD
Dh 3.3/8 × AVDD
Eh 3.4/8 × AVDD
Fh 3.5/8 × AVDD

5.6.1.22 USER (15h)

The USER register can be written to and read from.

Figure 5-45 USER Register Bit Allocation
7 6 5 4 3 2 1 0
USER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-25 USER Register Field Descriptions

Bit Field Value Description
7-0 USER N/A These bits are free for customer use. Their contents have no effect on device operation.

5.6.1.23 CONTROL (FFh)

Figure 5-46 CONTROL Register Bit Allocation
7 6 5 4 3 2 1 0
WED Not Implemented RED
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-26 CONTROL Register Field Descriptions

Bit Field Value Description
7 WED This bit determines whether write operations affect the contents of the volatile or non-volatile registers.
0h Not applicable (see below).
1h Data is copied from the RAM registers to the EEPROM registers. This bit is automatically reset upon completion of this task.
6-1 Not Implemented N/A These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
0 RED This bit determines whether read operations return the contents of the volatile or non-volatile registers.
0h Volatile register data is returned.
1h Non-volatile register data is returned.

5.6.2 VCOM Registers

5.6.2.1 VCOM DATA (Slave Address 28h, Register Address 00h)

The VCOM DATA register can be written to and read from.

Figure 5-47 VCOM DATA Register Bit Allocation
7 6 5 4 3 2 1 0
NI VCOM
R-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-27 VCOM DATA Register Bit Description

Bit Field Value Description
7 Not implemented N/A This bit is reserved for future use and should be programmed to 0 for proper operation.
6-0 VCOM Bits 6 through 0 set the value of the VCOM voltage.
N/A VCOM=(VCOM/127) × (VMAX–VMIN) + VMIN

5.6.2.2 VCOM CONTROL (Slave Address 28h, Register Address 02h)

The VCOM CONTROL register is write-only.

Figure 5-48 VCOM CONTROL Register Bit Allocation
7 6 5 4 3 2 1 0
SEL Not Implemented
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-28 VCOM CONTROL Register Bit Description

Bit Field Value Description
7 SEL The SEL bit determines whether read/write operations to the VCOM DATA register access the IVR, the WR, or both.
0 Write operations store data in the IVR and WR.
Read operations return the contents of the IVR.
1 Write operations store data in the WR only.
Read operations return the contents of the WR.
6-0 Not implemented N/A Bits 6 through 0 are reserved for future use. They should be programmed to 0 for proper operation.