JAJSP63A November   2023  – June 2024 TPS6522005-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6522005-EP default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.4 Application Curves

TPS6522005-EP Buck1 ramp
VIN = 5.0 V VOUT = 3.3V TA = 25 °C
Forced-PWM / High Bandwidth Iout = 1 A COUT_total = 57 μF
Figure 7-2 Buck1 ramp
TPS6522005-EP Buck3 ramp
VIN = 5.0 V VOUT = 3.3V TA = 25 °C
Forced-PWM / High Bandwidth Iout = 1 A COUT_total = 57 μF
Figure 7-4 Buck3 ramp
TPS6522005-EP LDO Fast Ramp
VIN = 5.0 V VOUT = 3.3V TA = 25 °C
LDO mode / Fast ramp Iout = 300 mA COUT_total = 10 μF
Figure 7-6 LDO Fast Ramp
TPS6522005-EP Bucks Discharge
VIN = 5.0 V VOUT = 3.3V TA = 25 °C
Forced-PWM / High Bandwidth no load COUT_total = 57 μF
Figure 7-8 Bucks Discharge
TPS6522005-EP Configurable power-up sequence - Example
Slot# Duration Assigned Rail
0 1.5 ms BUCK2
1 0 ms
2 3 ms LDO1 / LDO / GPO
3 1.5 ms
4 1.5 ms BUCK3
5 1.5 ms BUCK1
6 1.5 ms
7 10 ms
8 1.5 ms
9 10 ms nRSTOUT
10-15 0ms
Figure 7-10 Configurable power-up sequence - Example
TPS6522005-EP Buck2 ramp
VIN = 5.0 V VOUT = 3.3V TA = 25 °C
Forced-PWM / High Bandwidth Iout = 1 A COUT_total = 57 μF
Figure 7-3 Buck2 ramp
TPS6522005-EP LDO1 ramp
VIN = 5.0 V VOUT = 3.3V TA = 25 °C
LDO mode Iout = 400 mA COUT_total = 10 μF
Figure 7-5 LDO1 ramp
TPS6522005-EP LDO Slow Ramp
VIN = 5.0 V VOUT = 3.3V TA = 25 °C
LDO mode / Slow ramp Iout = 300 mA COUT_total = 10 μF
Figure 7-7 LDO Slow Ramp
TPS6522005-EP LDOs Discharge
VIN = 5.0 V VOUT = 3.3V TA = 25 °C
LDO mode no load COUT_total = 2.2 μF
Figure 7-9 LDOs Discharge
TPS6522005-EP Configurable power-down sequence - Example
Slot# Duration Assigned Rail
0 10 ms nRSTOUT / BUCK3
1 0 ms
2 10 ms BUCK1 / LDO1 / LDO / GPO
3 0 ms
4 10 ms BUCK2
5-15 0 ms
Figure 7-11 Configurable power-down sequence - Example