JAJSQ73C june   2014  – may 2023 TPS65263

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Enable and Adjusting UVLO
      3. 8.3.3  Soft-Start Time
      4. 8.3.4  Power-Up Sequencing
      5. 8.3.5  V7V Low Dropout Regulator and Bootstrap
      6. 8.3.6  Out-of-Phase Operation
      7. 8.3.7  Output Overvoltage Protection (OVP)
      8. 8.3.8  Pulse Skipping Mode (PSM)
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Overcurrent Protection
        1. 8.3.10.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.10.2 Low-Side MOSFET Overcurrent Protection
      11. 8.3.11 Power Good
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface Description
      2. 8.4.2 I2C Update Sequence
    5. 8.5 Register Maps
      1. 8.5.1 Register Description
      2. 8.5.2 VOUT1_SEL: Vout1 Voltage Selection Register (offset = 0x00H)
      3. 8.5.3 VOUT2_SEL: Vout2 Voltage Selection Register (offset = 0x01H)
      4. 8.5.4 VOUT3_SEL: Vout3 Voltage Selection Register (offset = 0x02H)
      5. 8.5.5 VOUT1_COM: Buck1 Command Register (offset = 0x03H)
      6. 8.5.6 VOUT2_COM: Buck2 Command Register (offset = 0x04H)
      7. 8.5.7 VOUT3_COM: Buck3 Command Register (offset = 0x05H)
      8. 8.5.8 SYS_STATUS: System Status Register (offset = 0x06H)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4 Power-Up Sequencing

The TPS65263 has dedicated enable pin and soft-start pin for each converter. The converter enable pins are biased by a current source that allows for easy sequencing by the addition of an external capacitor. Disabling the converter with an active pull-down transistor on the ENs pin allows for a predictable power-down timing operation. Figure 8-8 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at ENx pin.

A typical 1.4-µA current is charging ENx pin from input supply. When ENx pin voltage rise to typical 0.4 V, the internal V7V LDO turns on. A 3.8-µA pullup current is sourcing ENx. After ENx pin voltage reaches to ENx enabling threshold, 3-µA hysteresis current sources to the pin to improve noise sensitivity. The internal soft-start comparator compares SS pin voltage to 1.2 V. When SS pin voltage ramps up to 1.2 V, PGOOD monitor is enabled. After PGOOD deglitch time, PGOOD is deasserted. SS pin voltage eventually is clamped around
2.1 V.

GUID-20230504-SS0I-80WC-WHPD-MVTBLLS56D1Z-low.svg Figure 8-8 Startup Power Sequence