The TPS65987DDJ is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug and orientation detection for a USB Type-C and PD plug or receptacles. The TPS65987DDJ communicates with the cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port power switch, controls an external high current port power switch and negotiates alternate modes . The TPS65987DDJ may also control an attached super-speed multiplexer via GPIO or I²C to simultaneously support USB3.0/3.1 data rates and DisplayPort video.

The TPS65987DDJ is divided into five main sections:

• USB-PD controller
• cable plug and orientation detection circuitry
• port power switches
• power management circuitry
• digital core

The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD data is output through either the C_CC1 pin or the C_CC2 pin, depending on the orientation of the reversible USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and more detailed circuitry, see the USB-PD Physical Layer section.

The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and orientation detection, a description of its features and more detailed circuitry, see Port Power Switches.

The port power switches provide power to the system port through the VBUS pin and also through the C_CC1 or C_CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a description of its features and more detailed circuitry, see the Port Power Switches section.

The power management circuitry receives and provides power to the TPS65987DDJ internal circuitry and to the LDO_3V3 output. For a high-level block diagram of the power management circuitry, a description of its features and more detailed circuitry, see the Power Management section.

The digital core provides the engine for receiving, processing and sending all USB-PD packets as well as handling control of all other TPS65987DDJ functionality. A portion of the digital core contains ROM memory which contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the ROM called boot code, is capable of initializing the TPS65987DDJ, loading of device configuration information and loading any code patches into volatile memory in the digital core. For a high-level block diagram of the digital core, a description of its features and more detailed circuitry, see the Digital Core section.

The TPS65987DDJ is an I²C slave to be controlled by a host processor (see the I²C Interfaces section), and an SPI controller to write to and read from an optional external flash memory (see the SPI Controller Interface section).

The TPS65987DDJ also integrates a thermal shutdown mechanism (see theThermal Shutdown section) and runs off of accurate clocks provided by the integrated oscillators (see the Oscillators section).