JAJSNL3A December 2021 – May 2022 TPS7A13
A minimum input ceramic capacitor is required for stability. A minimum output ceramic capacitor is also required for stability; see the Section 6.3 table for the minimum capacitor values.
The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. A higher-value input capacitor may be necessary if large, fast rise-time load or line transients are anticipated, or if the device is located several inches from the input power source. Dynamic performance of the device is improved with the use of an output capacitor larger than the minimum value specified in the Section 6.3 table.
Although a bias capacitor is not required, good design practice is to connect a 0.1-μF ceramic capacitor from BIAS to GND. This capacitor counteracts reactive bias source effects if the source impedance is not sufficiently low. If the BIAS source is susceptible to fast voltage drops (for example, a 2-V drop in less than 1 µs) when the LDO load current is near the maximum value, the BIAS voltage drop may cause the output voltage to fall briefly. In such cases, use a BIAS capacitor large enough to slow the voltage ramp rate to less than 0.5 V/µs. For smaller or slower BIAS transients, any output voltage dips must be less than 5% of the nominal voltage.
Place the input, output, and bias capacitors as close as possible to the device to minimize the effects of trace parasitic impedance.