JAJSNL3A December   2021  – May 2022 TPS7A13

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excellent Transient Response
      2. 7.3.2 Global Undervoltage Lockout (UVLO)
      3. 7.3.3 Enable Input
      4. 7.3.4 Internal Foldback Current Limit
      5. 7.3.5 Active Discharge
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disable Mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
      2. 8.1.2  Input, Output, and Bias Capacitor Requirements
      3. 8.1.3  Dropout Voltage
      4. 8.1.4  Behavior During Transition From Dropout Into Regulation
      5. 8.1.5  Device Enable Sequencing Requirement
      6. 8.1.6  Load Transient Response
      7. 8.1.7  Undervoltage Lockout Circuit Operation
      8. 8.1.8  Power Dissipation (PD)
      9. 8.1.9  Estimating Junction Temperature
      10. 8.1.10 Recommended Area for Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • YCK|6
サーマルパッド・メカニカル・データ
発注情報

Input, Output, and Bias Capacitor Requirements

A minimum input ceramic capacitor is required for stability. A minimum output ceramic capacitor is also required for stability; see the Section 6.3 table for the minimum capacitor values.

The input capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. A higher-value input capacitor may be necessary if large, fast rise-time load or line transients are anticipated, or if the device is located several inches from the input power source. Dynamic performance of the device is improved with the use of an output capacitor larger than the minimum value specified in the Section 6.3 table.

Although a bias capacitor is not required, good design practice is to connect a 0.1-μF ceramic capacitor from BIAS to GND. This capacitor counteracts reactive bias source effects if the source impedance is not sufficiently low. If the BIAS source is susceptible to fast voltage drops (for example, a 2-V drop in less than 1 µs) when the LDO load current is near the maximum value, the BIAS voltage drop may cause the output voltage to fall briefly. In such cases, use a BIAS capacitor large enough to slow the voltage ramp rate to less than 0.5 V/µs. For smaller or slower BIAS transients, any output voltage dips must be less than 5% of the nominal voltage.

Place the input, output, and bias capacitors as close as possible to the device to minimize the effects of trace parasitic impedance.