JAJSIR7C October   2019  – August 2021 TPS8804

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Power-up
      2. 7.3.2 LDO Regulators
        1. 7.3.2.1 Power LDO Regulator
        2. 7.3.2.2 Internal LDO Regulator
        3. 7.3.2.3 Microcontroller LDO Regulator
      3. 7.3.3 Photo Chamber AFE
        1. 7.3.3.1 Photo Input Amplifier
        2. 7.3.3.2 Photo Gain Amplifier
      4. 7.3.4 LED Driver
        1. 7.3.4.1 LED Current Sink
        2. 7.3.4.2 LED Voltage Supply
      5. 7.3.5 Carbon Monoxide Sensor AFE
        1. 7.3.5.1 CO Transimpedance Amplifier
        2. 7.3.5.2 CO Connectivity Test
      6. 7.3.6 SLC Interface Transmitter and Receiver
        1. 7.3.6.1 SLC Transmitter
        2. 7.3.6.2 SLC Receiver
      7. 7.3.7 AMUX
      8. 7.3.8 Analog Bias Block and 8 MHz Oscillator
      9. 7.3.9 Interrupt Signal Alerts
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fault States
        1. 7.4.1.1 MCU LDO Fault
        2. 7.4.1.2 Over-Temperature Fault
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1  REVID Register (Offset = 0h) [reset = 0h]
      2. 7.6.2  STATUS1 Register (Offset = 1h) [reset = 0h]
      3. 7.6.3  STATUS2 Register (Offset = 2h) [reset = 0h]
      4. 7.6.4  MASK Register (Offset = 3h) [reset = 0h]
      5. 7.6.5  CONFIG1 Register (Offset = 4h) [reset = 20h]
      6. 7.6.6  CONFIG2 Register (Offset = 5h) [reset = 0h]
      7. 7.6.7  ENABLE1 Register (Offset = 6h) [reset = 0h]
      8. 7.6.8  ENABLE2 Register (Offset = 7h) [reset = 0h]
      9. 7.6.9  CONTROL Register (Offset = 8h) [reset = 0h]
      10. 7.6.10 GPIO_AMUX Register (Offset = Bh) [reset = 0h]
      11. 7.6.11 COSW Register (Offset = Ch) [reset = 0h]
      12. 7.6.12 CO Register (Offset = Dh) [reset = 0h]
      13. 7.6.13 LEDLDO Register (Offset = Fh) [reset = 0h]
      14. 7.6.14 PH_CTRL Register (Offset = 10h) [reset = 0h]
      15. 7.6.15 LED_DAC_A Register (Offset = 11h) [reset = 0h]
      16. 7.6.16 LED_DAC_B Register (Offset = 12h) [reset = 0h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Photo Amplifier Component Selection
        2. 8.2.2.2 LED Driver Component Selection
        3. 8.2.2.3 LED Voltage Supply Selection
        4. 8.2.2.4 Regulator Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Photo Amplifier Layout
      2. 10.1.2 CO Amplifier Layout
      3. 10.1.3 Ground Plane Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE AND CURRENTS
VPWRUP Power up threshold. Note: Device enters active state when MCU_PG=1. VCC rising 1.2 1.55 2.0 V
VPWRDOWN Power down threshold VCC falling 0.932 1.15 2.0 V
VPWR, HYS VCC power up to power down hysteresis 6.4 400 580 mV
VVCCLOW, RISE VCC low warning reset threshold PLDO voltage rising 2.35 2.54 2.7 V
Deglitch time 110 141 172 µs
VVCCLOW, FALL VCC low warning assert threshold PLDO voltage falling 2.15 2.42 2.6 V
Deglitch time 110 141 172 µs
ISTANDBY Standby Supply Current  All blocks that can be disabled are off, TJ=27C, VCC=3V, VMCU=1.8V 3.8 4.4 µA
All blocks that can be disabled are off, TJ=27C, VCC=9V, VMCU=3.3V 7.7 9.1 µA
POWER LDO
VPLDO Output Voltage VCC = 2.0 V, IPLDO = 10 mA 1.93 1.96 1.99 V
VCC = 2.0 V, IPLDO = 30 mA 1.8 1.89 1.95 V
VCC = 3.3 V, IPLDO = 30 mA 3.1 3.22 3.3 V
VCC = 9 V, IPLDO = 30 mA 4.1 4.9 6.7 V
VCC = 11.5 V, IPLDO = 30 mA 4.1 5 6.7 V
CPLDO PLDO capacitor required for stability 0.7 1 1.3 µF
INTERNAL LDO
VINTLDO Output Voltage IVINT < 10 mA 2.25 2.3 2.35 V
IVINT < 10 uA, T>80C 2.25 2.3 2.40 V
DC Output Voltage Accuacy No external/internal load, VCC = 2.6 V - 11.5 V –2 2 %
Line Regulation VCC = 2.6 V-11.5 V, IOUT = 10 mA –2 2 %
Load Regulation IVINT = 0 mA - 10 mA, VCC = 3 V –2 2 %
Transient regulation IVINT stepped from 0 mA to 10 mA in 1us –8 8 %
IVINT stepped from 10 mA to 0 mA in 1us –5 5 %
PSRR VIN = 3.0 V, IOUT = 10 mA, f = 60 Hz (200 mVpp) 50 dB
IINTLDO, OUT Output current range 0 10 mA
IINTLDO, SC Short Circuit Current Limit 30 280 500 mA
VINTLDO, DO Dropout Voltage From PLDO to VINT, IVINT = 10 mA, PLDO = 2.2 V 52 66 mV
CINTLDO, OUT Output Capacitor Ceramic 0.7 1 1.3 µF
ESR of Output Capacitor 100 mΩ
MCU LDO
VMCULDO Output Voltage(1) IMCULDO < 30 mA, VCC > 2.2 V, VMCUSET = 00 (T < 80°C for no load) 1.425 1.5 1.575 V
IMCULDO < 10 uA, VCC > 2.2 V, VMCUSET = 00, T > 80°C 1.425 1.5 1.65 V
IMCULDO < 30 mA, VCC > 2.6 V, VMCUSET = 01  (T < 80°C for no load) 1.71 1.8 1.89 V
IMCULDO < 10 uA, VCC > 2.6 V, VMCUSET = 01, T > 80°C 1.71 1.8 1.98 V
IMCULDO < 30 mA, VCC > 3.65 V, VMCUSET = 10  (T < 80°C for no load) 2.38 2.5 2.63 V
IMCULDO < 10 uA, VCC > 3.65 V, VMCUSET = 10, T > 80°C 2.38 2.5 2.75 V
IMCULDO < 10 mA, VCC > 3.65 V, VMCUSET = 11  (T < 80°C for no load) 3.13 3.3 3.47 V
IMCULDO < 10 uA, VCC > 4.5 V, VMCUSET = 11, T > 80°C 3.13 3.3 3.60 V
IMCULDO < 50 mA, VCC > 5.5 V, VMCUSET = 11 3.13 3.3 3.47 V
DC Output Voltage Accuracy T < 80°C –5 5 %
VMCULDO,PG MCULDO power good threshold VMCU rising 75 82 95 %
VMCU falling 65 78 85 %
IMCULDO Output Current Range VCC > 2.2 V, VMCUSET = 00 0 30 mA
VCC > 2.6 V, VMCUSET = 01 0 30 mA
VCC > 3.65 V, VMCUSET = 10 0 30 mA
VCC > 4.5 V, VMCUSET = 11 0 50 mA
VMCULDO, TR MCULDO load transient regulation IMCULDO stepped from 0 mA to 10 mA in 1us, T < 80°C –7 7 %
IMCULDO stepped from 0 mA to 10 mA in 1us, T > 80°C –8 8 %
IMCULDO stepped from 10 mA to 0 mA in 1us, T < 80°C –5 5 %
IMCULDO stepped from 10 mA to 0 mA in 1us, T > 80°C –8 8 %
IMCULDO, SC Short Circuit current limit 72 162 253 mA
tMCULDO, PWR Power Up Time CMCULDO = 1µF, time from VMCU=0V to 90% of target voltage 600 1100 µs
TMCULDO, PG MCULDO power good deglitch time 92 125 158 µs
TMCULDO, MASK MCULDO low voltage error mask time. MCULDO_ERR is masked for T_MCULDO,MASK after VMCUSET or MCU_DIS is changed. 10 ms
IMCULDO, Q Quiescent Current  IMCULDO = 0µA 2.04 3 µA
CMCULDO Output Capacitor Ceramic 0.7 1 10 µF
ESR of Output Capacitor 100 mΩ
RMCUSEL MCUSEL component requirements. Not tested in production Pull-down resistance to set VMCUSET[1:0]=00 on powerup 558 620 682 Ω
Pull-down resistance to set VMCUSET[1:0]=01 on powerup 0 10 Ω
Pull-up resistance to VINT to set VMCUSET[1:0]=10 on powerup 0 10 Ω
Capacitance to set VMCUSET[1:0]=11 on powerup 300 1000 pF
PHOTO CHAMBER INPUT STAGE AMPLIFIER
VPDO Output voltage range PAMP_EN=1, Feedback network: 1.5M Ω, 10pF 0 0.5 V
fPDIN, BW Unity Gain Bandwidth 1 5 MHz
VPDIN, OFS Input Offset Voltage  -530 -195 240 µV
VPDO, OFS Output Offset Voltage 50mV applied to PDP with 1.5MΩ series resistor. 1.5MΩ resistor connects PDN to PDO. Voltage measured between 50mV and PDO. -10 10 mV
fPDIN, CHOP Chop Frequency 2 MHz
TPDIN, SET Input amplifier settling time. Time between stepping the current and measuring 90% of the final value + 10% of the initial value at PDO Feedback network: 1.5M Ω, 10pF. 1 nA to 10 nA applied from PDN to PDP. 0V reference 0 30 40 µs
Feedback network: 1.5MΩ, 5pF. 1.5MΩ  connected from PDP to PREF. 1 nA to 10 nA applied from PDN to PDP. PREF_SEL=1 0 20 40 µs
IPDIN, ACT Active current. Current does not include bias block or 8 MHz oscillator. 175 210 µA
PHOTO CHAMBER GAIN STAGE AMPLIFIER
GPGAIN Closed Loop Gain Slope (VAOUT_PH2-VAOUT_PH1)/(VSIG2-VSIG1). Apply VSIG1 from PREF to PDO and measure AOUT_PH. Apply VSIG2 from COTEST to PDO and measure AOUT_PH VPDO1=10mV,  VPDO2=20mV, PREF_SEL=0, PGAIN[1:0] = 00 4.75 4.9 5.05 V/V
VPDO1=10mV,  VPDO2=20mV, PREF_SEL=0, PGAIN[1:0] = 01 10.67 11 11.33 V/V
VPDO1=10mV,  VPDO2=20mV, PREF_SEL=0, PGAIN[1:0] = 10 19.4 20 20.6 V/V
VPDO1=10mV,  VPDO2=20mV, PREF_SEL=0, PGAIN[1:0] = 11 33.95 35 36.05 V/V
Closed Loop Gain Slope (VAOUT_PH2-VAOUT_PH1)/(VSIG2-VSIG1). Apply VSIG1 from PREF to PDO and measure AOUT_PH. Apply VSIG2 from PREF to PDO and measure AOUT_PH VSIG1=10mV,  VSIG2=20mV, PREF_SEL=1, PGAIN[1:0] = 00 4.61 4.75 4.89 V/V
VSIG1=10mV,  VSIG2=20mV, PREF_SEL=1, PGAIN[1:0] = 01 10.09 10.4 10.71 V/V
VSIG1=10mV,  VSIG2=20mV, PREF_SEL=1, PGAIN[1:0] = 10 17.94 18.5 19.06 V/V
VSIG1=10mV,  VSIG2=20mV, PREF_SEL=1, PGAIN[1:0] = 11 31.28 32.25 33.22 V/V
FPGAIN, BW Unity Gain Bandwidth 1 5 8 MHz
VPGAIN, OFS Input offset Voltage -6 5 mV
TPGAIN, SET Gain amplifier settling time. Time between stepping the voltage and measuring 90% of the final value + 10% of the initial value at AOUT_PH PGAIN[1:0]=00. PDO stepped from 3mV to 30mV. PREF_SEL=0 1.8 2.522 µs
IPGAIN, ACT Active current. Current does not include bias block. 1.0 V input voltage, PGAIN[1:0] = 00, PGAIN_EN = 1 40 70 µA
LED LDO
VLEDLDO LEDLDO output voltage range 7.5 10 V
VLEDLDO,ACC LDO output accuracy I_LEDLDO = 0uA to 100uA -5 5 %
VLEDLDO, RES LED LDO output step size 0.5 V
ILEDLDO, OUT LDO output current limit 1 3 6 mA
ILEDLDO, Q Quiescent current. Current does not include bias block. 31 60 µA
VLEDLDO, DROP LED LDO dropout voltage VSLC=7V, ILEDLDO=100uA 565 1000 mV
LED DRIVER A
NPDACA, RES Resolution 8 Bits
VCSA CSA output voltage TJ = 27°C TEMPCOA[1:0] = 00, PDAC_A = 00, RCSA=1 kOhms, VDINA=3V 274 299 323 mV
TJ = 27°C TEMPCOA[1:0] = 00, PDAC_A = FF, RCSA=1 kOhms, VDINA=3V 567 593 619 mV
TJ = 27°C TEMPCOA[1:0] = 01, PDAC_A = 00, RCSA=1 kOhms, VDINA=3V 252 277 301 mV
TJ = 27°C TEMPCOA[1:0] = 01, PDAC_A = FF, RCSA=1 kOhms, VDINA=3V 546 572 597 mV
TJ = 27°C TEMPCOA[1:0] = 10, PDAC_A = 00, RCSA=1 kOhms, VDINA=3V 164 188 213 mV
TJ = 27°C TEMPCOA[1:0] = 10, PDAC_A = FF, RCSA=1 kOhms, VDINA=3V 458 484 510 mV
TJ = 27°C TEMPCOA[1:0] = 11, PDAC_A = 00, RCSA=1 kOhms, VDINA=3V 54 79 104 mV
TJ = 27°C TEMPCOA[1:0] = 11, PDAC_A = FF, RCSA=1 kOhms, VDINA=3V 350 376 403 mV
VPDACA, STEP DAC step size 1.18 mV
INL -10 10 LSB
DNL -1.5 1.5 LSB
tPDACA, SET Settling Time 1 5 µs
KPDACA, COMP CSA temperature compensation coefficient TEMPCOA[1:0] = 00, PDAC_A[7:0] = 0x00, RCSA=1 kOhms, VDINA=3V, TJ=0°C, 50°C 0.174 0.347 0.521 mV/°C
TEMPCOA[1:0] = 01, PDAC_A[7:0] = 0x00, RCSA=1 kOhms, VDINA=3V, TJ=0°C, 50°C 0.208 0.416 0.624 mV/°C
TEMPCOA[1:0] = 10, PDAC_A[7:0] = 0x00, RCSA=1 kOhms, VDINA=3V, TJ=0°C, 50°C 0.346 0.693 1.039 mV/°C
TEMPCOA[1:0] = 11, PDAC_A[7:0] = 0x00, RCSA=1 kOhms, VDINA=3V, TJ=0°C, 50°C 0.520 1.040 1.560 mV/°C
VDINA, DROP Dropout voltage. Voltage required between DINA and CSA for current regulation. PLDO=3.6V, RCSA=820mΩ, TEMPCOA[1:0]=11, PDAC_A[7:0]=0x28, TJ=27°C (I_LED≈158mA, 0.8% temp coefficient) 300 mV
PLDO=3.6V, RCSA=820mΩ, TEMPCOA[1:0]=01, PDAC_A[7:0]=0x79, TJ=27°C (I_LED≈507mA, 0.1% temp coefficient) 500 mV
IDINA LED current 0 550 mA
LED DRIVER B
NPDACB, RES Resolution 8 Bits
VCSB CSB output voltage TJ = 27°C TEMPCOB[1:0] = 00, PDAC_B = 00, RCSB=1 kOhms, VDINB=3V 271 299 327 mV
TJ = 27°C TEMPCOB[1:0] = 00, PDAC_B = FF, RCSB=1 kOhms, VDINB=3V 562 594 626 mV
TJ = 27°C TEMPCOB[1:0] = 01, PDAC_B = 00, RCSB=1 kOhms, VDINB=3V 250 277 305 mV
TJ = 27°C TEMPCOB[1:0] = 01, PDAC_B = FF, RCSB=1 kOhms, VDINB=3V 541 572 604 mV
TJ = 27°C TEMPCOB[1:0] = 10, PDAC_B = 00, RCSB=1 kOhms, VDINB=3V 163 189 216 mV
TJ = 27°C TEMPCOB[1:0] = 10, PDAC_B = FF, RCSB=1 kOhms, VDINB=3V 456 486 516 mV
TJ = 27°C TEMPCOB[1:0] = 11, PDAC_B = 00, RCSB=1 kOhms, VDINB=3V 55 81 108 mV
TJ = 27°C TEMPCOB[1:0] = 11, PDAC_B = FF, RCSB=1 kOhms, VDINB=3V 350 379 408 mV
VPDACB, STEP DAC step size 1.18 mV
INL -10 10 LSB
DNL -1.5 1.5 LSB
tPDACB, SET Settling time 1 5 µs
KPDACB, COMP CSB temperature compensation coefficient TEMPCOB[1:0] = 00, PDAC[7:0] = 0x00, RCSB=1 kOhms, VDINB=3V, TJ=0°C, 50°C 0.174 0.347 0.521 mV/°C
TEMPCOB[1:0] = 01, PDAC[7:0] = 0x00, RCSB=1 kOhms, VDINB=3V, TJ=0°C, 50°C 0.208 0.416 0.624 mV/°C
TEMPCOB[1:0] = 10, PDAC[7:0] = 0x00, RCSB=1 kOhms, VDINB=3V, TJ=0°C, 50°C 0.346 0.693 1.039 mV/°C
TEMPCOB[1:0] = 11, PDAC[7:0] = 0x00, RCSB=1 kOhms, VDINB=3V, TJ=0°C, 50°C 0.520 1.040 1.560 mV/°C
VDINB, DROP Dropout voltage. Voltage required between DINB and CSB for current regulation. PLDO=3.6V, RCSA=820mΩ, TEMPCOB[1:0]=11, PDAC[7:0]=0x28, TJ=27°C (I_LED≈158mA, 0.8% temp coefficient) 300 mV
PLDO=3.6V, RCSA=820mΩ, TEMPCOB[1:0]=01, PDAC[7:0]=0x79, TJ=27°C (I_LED≈507mA, 0.1% temp coefficient) 500 mV
IDINB LED current 0 550 mA
CO TRANSIMPEDANCE AMPLIFIER
RI, CO CO input resistance COSWRI = 1 0.7 1 1.5 kΩ
RF, CO CO feedback resistance COGAIN[1:0] = 00, COSWRG = 1 770 1100 1430 kΩ
COGAIN[1:0] = 01, COSWRG = 1 210 300 390 kΩ
COGAIN[1:0] = 10, COSWRG = 1 350 500 650 kΩ
COGAIN[1:0] = 11, COSWRG = 1 560 800 1040 kΩ
VIN, COP CO amplifier input voltage (COP pin) 0 0.6 V
VIN, CON CO amplifier input voltage (CON pin) 0 0.6 V
VOFFS, CO CO amplifier input offset voltage  -130 94 300 µV
VOUT, COO CO amplifier output voltage (COO pin) 0.1 2 V
ICO, Q CO amplifier quiescent current  0.63 2.1 µA
fCO, BW CO amplifier unity gain bandwidth 5 12 20 kHz
fCO, CHOP CO amplifier chop frequency 3.8 4 4.2 kHz
RCOO CO amplifier output resistance COSWRO = 1 70 95 130 kΩ
VCOPREF CO amplifier reference voltage COSWREF=1, COREF[1:0] = 00, TJ = 27°C 0.89 1.14 1.47 mV
COSWREF=1, COREF[1:0] = 00, TJ = -40°C to 85°C 0.86 1.14 1.66
COSWREF=1, COREF[1:0] = 01, TJ = 27°C 1.75 2.23 2.7
COSWREF=1, COREF[1:0] = 01, TJ = -40°C to 85°C 1.7 2.23 2.95
COSWREF=1, COREF[1:0] = 10, TJ = 27°C 2.6 3.23 4
COSWREF=1, COREF[1:0] = 10, TJ = -40°C to 85°C 2.55 3.23 4.24
COSWREF=1, COREF[1:0] = 11, TJ = 27°C 3.45 4.43 5.38
COSWREF=1, COREF[1:0] = 11, TJ = -40°C to 85°C 3.4 4.43 5.48
RCOTEST, PU COTEST pull up FET resistance 0.36 0.76 1.1 kΩ
RCOTEST, PD COTEST pull-down FET resistance 0.25 0.37 0.82 kΩ
SLC INTERFACE
tSLCRX, DEG SLC receiver deglitch time SLCRX_EN=1, SLCRX_DEG[1:0]=00 0 0 0.065 ms
SLCRX_EN=1, SLCRX_DEG[1:0]=01 0.090 0.125 0.160
SLCRX_EN=1, SLCRX_DEG[1:0]=10 0.9 1 1.1
SLCRX_EN=1, SLCRX_DEG[1:0]=11 19.8 20 20.2
ISLCRX, Q SLC receiver standby current SLCRX_EN = 1 0.25 0.5 uA
VSLCRX,IHI SLC receiver input high threshold voltage SLCRX_HYS=0 1.3 2.0 2.7 V
SLCRX_HYS=1 1.3 2.0 2.7 V
VSLCRX,ILO SLC receiver input low threshold voltage SLCRX_HYS=0 0.5 0.8 1.1 V
SLCRX_HYS=1 1.2 1.8 2.7 V
VSLCRX,HYS  SLC receiver input hysteresis  SLCRX_HYS=0 0.7 1.2 1.7 V
SLCRX_HYS=1 0.01 0.2 0.3 V
RSLCRX,PD SLC receiver input pulldown resistance SLCRX_PD=1 65 107 165 kΩ
SLCRX_PD=0 3.5 41 56 MΩ
VSLCTXx ,OH SLC transmitter output high voltage VSLC=11.5V, ISLC_TXx=−16mA 11.0 11.3 11.5  V
VSLCTXx,OL SLC transmitter output low voltage VSLC=11.5V, ISLC_TXx=16mA 0  0.1 0.5 V
ANALOG MULTIPLEXER
VMUX Multiplexer buffer input signal voltage range AMUX_BYP=0 0.05 2 V
GMUX, GAIN Multiplexer bufffer output gain AMUX_BYP=0 0.99 1 1.01 V/V
VMUX, OFFS Multiplexer buffer offset voltage  AMUX_BYP=0 -8 -0.5 8 mV
tMUX, EN Multiplexer buffer enable settling time AMUX_BYP=0, AMUX_SEL stepped from 000 to 011 with PDO=2V, PAMP_EN=0. Time until AMUX reaches 99% of its final value 0 10 15 us
tMUX, STEP Multiplexer buffer input step settling time AMUX_BYP=0, AMUX_SEL=011, PDO stepped from 50mV to 2V, PAMP_EN=0. Time until AMUX reaches 99% of its final value 0 10 15 us
fMUX, BW Multiplexer bandwidth AMUX_BYP=0 0.5 1 25 MHz
IMUX, OUT Multiplexer output current AMUX_BYP=0 –10 10 uA
IMUX, Q Multiplexer quiescent current. Current does not include bias block. AMUX_BYP=0 8.3 50 uA
CMUX Multiplexer buffer output capacitor required for stability AMUX_BYP=0 150 1000 pF
OSCILLATOR, REFERENCE SYSTEM
fOSC8 Oscillator frequency 8 MHz
Frequency accuracy TA = -10°C to 70°C –3 3 %
fOSC32 Low-power Oscillator frequency 32 kHz
Frequency accuracy TA = -10°C to 70°C –3 3 %
TTIMEOUT Error timeout time 0.9 1 1.1 s
IREF0P3, Q REF0P3 buffer quiescent current VCC current difference between REF0P3_EN=0 and REF0P3=1. IREF0P3=0 µA 0.38 0.76 µA
CREF0P3 REF0P3 output capacitor required for stability 0.7 1 1.5 nF
TREF0P3, SET REF0P3 settling time From REF0P3 enabled to 99% of final output voltage. CREF0P3=1nF, IREF0P3=0 µA 1 1.8 ms
VREF0P3, OUT REF0P3 output voltage IREF0P3 = 10 µA 270 300 330 mV
IREF0P3 = -25 µA 270 300 330 mV
IVCCLOW,Q VCC_LOW monitor quiescent current 0.9 2 uA
IO BUFFERS
VIO, ILO IO buffer input low threshold LEDEN, CSEL, MCU_TX1, MCU_TX2, GPIO 0.3×VMCU 0.7× VMCU V
VIO, IHI IO buffer input high threshold LEDEN, CSEL, MCU_TX1, MCU_TX2, GPIO 0.3×VMCU 0.7× VMCU V
IIO, LEAK IO buffer input leakage current LEDEN 100 nA
MCU_TX1 100 nA
CSEL 100 nA
VIO, OL IO buffer output low-level MCU_RX, GPIO. IIO = 3 mA, VMCU = 1.8 V 0 0.19 0.6 V
MCU_RX, GPIO. IIO = 1 mA, VMCU = 1.5 V 0 0.20 0.6 V
VIO, OH IO buffer output high-level. Spec is the voltage drop from VMCU (i.e. VMCU - VOH) MCU_RX, GPIO. IIO = -3 mA, VMCU = 1.8 V 0 0.30 0.6 V
MCU_RX, GPIO. IIO = -1 mA, VMCU = 1.5 V 0 0.37 0.6 V
CIN, IO Input capacitance LEDEN, CSEL 2 10 pF
CIN, IO Input capacitance MCU_TX1, MCU_TX2 2 10 pF
CIN, IO Pin capacitance MCU_RX, GPIO 2 10 pF
RIO,PD IO pulldown resistor MCU_RX, GPIO 0.8 10 50 MΩ
THERMAL WARNING
TWARNING Thermal trip point 110 C
THERMAL SHUTDOWN
TSHTDWN Thermal trip point 125 C
Thermal hysteresis 5 15 20
tOTS,MASK Thermal error mask time. OTS_ERR is masked for tOTS,MASK after device fully powers up or OTS_EN set to 1 300 350 us
I2C IO
VI2C,IL Low-level input voltage   -0.5   0.3 × VMCU V
VI2C,IH High-level input voltage 0.7 × VMCU     V
VI2C,HYS Hysteresis of Schmitt trigger
inputs		   0.05 × VMCU     V
VI2C,OL Low-level output voltage 3 mA sink current; VMCU >2V 0   0.4 V
2 mA sink current; VMCU < 2V 0   0.2 × VMCU V
II2C,OL Low-level output current VOL = 0.4 V 2.5     mA
VOL = 0.6 V 4     mA
II2C,IN Input current to each I/O pin 0.1VMCU < VI < 0.9VMCUmax -10   10 µA
CI2C,IN Capacitance for each I/O pin       10 pF
tI2C,OF Output fall time From VIHmin to VILmax, Standard-Mode     250 ns
From VIHmin to VILmax, Fast-Mode   250 ns
tI2C,SP Pulse width of spikes that must be suppressed by the input filter   0   50 ns
I2C BUS LINES
fSCL SCL clock frequency, Standard-Mode   0   100 kHz
SCL clock frequency Fast-Mode   0   400 kHz
tHD;STA hold time (repeated) START condition, Standard-Mode After this period, the first clock pulse is generated. 4   µs
hold time (repeated) START condition, Fast-Mode After this period, the first clock pulse is generated. 0.6   µs
tSCL ,LOW LOW period of the SCL clock, Standard-Mode 4.7   µs
LOW period of the SCL clock, Fast-Mode   1.3   µs
tSCL,HIGH HIGH period of the SCL clock, Standard-Mode   4   µs
HIGH period of the SCL clock, Fast-Mode   0.6   µs
tSU;STA set-up time for a repeated START condition, Standard-Mode   4.7   µs
set-up time for a repeated START condition, Fast-Mode   0.6   µs
tHD;DAT data hold time, Standard-Mode CBUS compatible masters 5   µs
tHD;DAT I2C-bus devices 0   µs
tHD;DAT data hold time, Fast-Mode CBUS compatible masters 0   µs
tHD;DAT I2C-bus devices 0   µs
tSU;DAT data set-up time, Standard-Mode   250   ns
data set-up time, Fast-Mode   100   ns
tI2C,RISE rise time of both SDA and SCL signals, Standard-Mode     1000 ns
rise time of both SDA and SCL signals, Fast-Mode   20   300 ns
tI2C,FALL fall time of both SDA and SCL signals, Standard-Mode     300 ns
fall time of both SDA and SCL signals, Fast-Mode   20 × (VMCU / 5.5 V)   300 ns
tSU;STO set-up time for STOP condition, Standard-Mode   4 µs
set-up time for STOP condition, Fast-Mode   0.6   µs
tBUF bus free time between a STOP and START condition, Standard-Mode   4.7   µs
bus free time between a STOP and START condition, Fast-Mode   1.3   µs
tVD;DAT data valid time, Standard-Mode       3.45 µs
data valid time, Fast-Mode       0.9 µs
tVD;ACK data valid acknowledge time, Standard-Mode       3.45 µs
data valid acknowledge time, Fast-Mode       0.9 µs
CBUS capacitive load for each bus line, Standard-Mode       400 pF
capacitive load for each bus line, Fast-Mode       250 pF
VNL noise margin at the LOW level for each connected device (including hysteresis) 0.1 × VMCU   V
VNH noise margin at the HIGH level for each connected device (including hysteresis) 0.2 × VMCU   V
(1) MCU LDO output voltage on power-up is determined by the MCUSEL pin state.