JAJSGE2 October   2018 TPS92515AHV-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     降圧LEDドライバ・アプリケーションの概略図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  General Operation
      2. 8.3.2  Current Sense Comparator
      3. 8.3.3  OFF Timer
      4. 8.3.4  OFF-Timer, Shunt FET Dimming or Shunted Output Condition
      5. 8.3.5  Internal N-channel MOSFET
        1. 8.3.5.1 Drop-Out
      6. 8.3.6  VCC Internal Regulator and Undervoltage Lockout (UVLO)
      7. 8.3.7  Analog Adjust Input
        1. 8.3.7.1 IADJ Pin Clamp
        2. 8.3.7.2 IADJ Pin Clamp Characteristic
        3. 8.3.7.3 Analog Adjust (IADJ Pin) Control Methods
        4. 8.3.7.4 IADJ Control Method Notes
      8. 8.3.8  Thermal Protection
        1. 8.3.8.1 Maximum Output Current and Junction Temperature
      9. 8.3.9  Junction Temperature Relative Estimation
      10. 8.3.10 BOOT and BOOT UVLO
        1. 8.3.10.1 Start-Up, BOOT-UVLO and Pre-Charged Condition
      11. 8.3.11 PWM (UVLO and Enable)
        1. 8.3.11.1 Using PWM for UVLO (Undervoltage Lockout) Protection
          1. 8.3.11.1.1 UVLO Programming Resistors
        2. 8.3.11.2 Using PWM for Digitally Controlled Enable
        3. 8.3.11.3 UVLO: VIN, VCC and BOOT UVLO
        4. 8.3.11.4 Analog and PWM Dimming - Normalized Results and Comparison
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 General Design Procedure
        1. 9.2.1.1 Calculating Duty Cycle
        2. 9.2.1.2 Calculate OFF-Time Estimate
        3. 9.2.1.3 Calculate OFF-Time Resistor ROFF
        4. 9.2.1.4 Calculate the Minimum Inductance Value
        5. 9.2.1.5 Calculate the Sense Resistance
        6. 9.2.1.6 Calculate Input Capacitance
        7. 9.2.1.7 Calculate Output Capacitance
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Calculating Duty Cycle
        2. 9.2.3.2 Calculate OFF-Time Estimate
        3. 9.2.3.3 Calculate OFF-Time Resistor ROFF
        4. 9.2.3.4 Calculate the Inductance Value
        5. 9.2.3.5 Calculate the Sense Resistance
        6. 9.2.3.6 Calculate Input Capacitance
        7. 9.2.3.7 Verify Peak Current for Inductor Selection
        8. 9.2.3.8 Calculate Output Capacitance
        9. 9.2.3.9 Calculate UVLO Resistance Values
      4. 9.2.4 Application Curves
    3. 9.3 Dos and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Input Source Direct from Battery
    2. 10.2 Input Source from a Boost Stage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
        1. 12.1.1.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.1 Layout Guidelines

The performance of any switching converter depends as much upon the layout of the PCB as it does on the component selection. Follow these simple guidelines to maximize noise rejection and minimize the generation of EMI within the circuit.

Figure 44 shows a sample layout and the associated current loops.

  • Discontinuous currents are the type of current most likely to generate EMI. Be careful when routing these paths.
    • The main path for discontinuous current contains the input capacitor (CIN), the recirculating diode (D1), the internal MOSFET (DRN pin to SW pin), and the sense resistor (RSENSE) shown as LOOP2. Make LOOP2 as small as possible.
    • Make the connections between all three components short and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and the SW pin connect, shown as LOOP1). Make them large enough to connect the components without producing excessive heat from the current it carries.
  • The IADJ, COFF, CSN and VIN pins are all high-impedance control inputs, therefore minimize the loops containing these high impedance nodes. The most sensitive loop contains the sense resistor (RSENSE) Place the sense resistor as close as possible to the CSN and VIN pins to maximize noise rejection.
  • Place the OFF-time capacitor (connected from the COFF pin to ground) close to the COFF and GND pins to maximize noise rejection.
  • External resistors (if used) bias the IADJ pin. Place them close to the IADJ and GND pins and use a small capacitor to decouple.
  • In some applications the LED load can be far away (several inches or more) from the device, or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED load is large or separated from the main converter, place the output capacitor close to the LEDs to reduce the effects of parasitic inductance on the AC impedance of the capacitor.