JAJSSC7 December   2023 TPSI3100

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Over-current Fault Error
        5. 9.2.2.5 Over-current Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DVX|16
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20210913-SS0I-1JCS-2HZV-GDX7QXGR6LDV-low.svg Figure 5-1 TPSI310x and TPSI310xLDVX Package, 16-Pin SSOP(Top View)
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I - Active high driver enable. Internal 500 kΩ pull-down to VSSP.
2 CE I - Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500 kΩ pull-down to VSSP.
3 VSSP - GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground.
4 VDDP - P Power supply for the primary side.
5 PGOOD O - Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
6 FLT1 O - Fault 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
7 ALM1 O - Alarm 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
8 VSSP - GND Ground supply for the primary side. All VSSP must be connected to the primary side ground.
9 VSSS - GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.
10 RESP O - Used in conjunction with an external resistor connected to VSSS to adjust comparator response time. When not being used, tie to VSSS.
11 ALM1_CMP I - Analog comparator input. When ALM1_CMP voltage exceeds internal reference voltage, ALM1 is asserted low within tALM_LATENCY. Internal 3 MΩ pull-down to VSSS. When not being used, tie to VSSS.
12 FLT1_CMP I - Analog comparator input. When FLT1_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low regardless of EN state and FLT1 asserted low within tFLT_LATENCY. Internal 3 MΩ pull-down to VSSS. When not being used, tie to VSSS.
13 VDDM - P Generated mid-supply, nominal 5 V.
14 VSSS - GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground.
15 VDDH - P Generated high supply, nominal 15.8 V.
16 VDRV O - Active high driver output.
(1) P = power, GND = ground, NC = no connect
GUID-20220801-SS0I-4GPR-ZBX8-GPKMDVZS3Z0Q-low.svg Figure 5-2 TPSI311x and TPSI311xLDVX Package, 16-Pin SSOP(Top View)
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I - Active high driver enable. Internal 500 kΩ pull-down to VSSP.
2 CE I - Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500 kΩ pull-down to VSSP.
3 VSSP - GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground.
4 VDDP - P Power supply for the primary side.
5 PGOOD O - Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
6 FLT1 O - Fault 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
7 FLT2 O - Fault 2 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
8 VSSP - GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground.
9 VSSS - GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.
10 RESP O - Used in conjunction with an external resistor connected to VSSS to adjust comparator response time. When not being used, tie to VSSS.
11 FLT2_CMP I - Analog comparator input. When FLT2_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low regardless of EN state and FLT2 asserted low within tFLT_LATENCY. Internal 3 MΩ pull-down to VSSS. When not being used, tie to VSSS.
12 FLT1_CMP I - Analog comparator input. When FLT1_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low regardless of EN state and FLT1 asserted low within tFLT_LATENCY. Internal 3 MΩ pull-down to VSSS. When not being used, tie to VSSS.
13 VDDM - P Generated mid-supply, nominal 5 V.
14 VSSS - GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground.
15 VDDH - P Generated high supply, nominal 15.8 V.
16 VDRV O - Active high driver output.
GUID-20220801-SS0I-WQKM-GNCP-CBQQZ8WZ8Z5X-low.svg Figure 5-3 TPSI312x DVX Package, 16-Pin SSOP(Top View)
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I - Active high driver enable. Internal 500 kΩ pull-down to VSSP.
2 CE I - Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500 kΩ pull-down to VSSP.
3 VSSP - GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground.
4 VDDP - P Power supply for the primary side.
5 PGOOD O - Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
6 ALM1 O - Alarm 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
7 ALM2 O - Alarm 2 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
8 VSSP - GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground.
9 VSSS - GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.
10 RESP O - Used in conjunction with an external resistor connected to VSSS to adjust comparator response time. When not being used, tie to VSSS.
11 ALM2_CMP I - Analog comparator input. When ALM2_CMP voltage exceeds internal reference voltage, ALM2 is asserted low within tALM_LATENCY. Internal 3 MΩ pull-down to VSSS. When not being used, tie to VSSS.
12 ALM1_CMP I - Analog comparator input. When ALM1_CMP voltage exceeds internal reference voltage, ALM1 is asserted low within tALM_LATENCY. Internal 3 MΩ pull-down to VSSS. When not being used, tie to VSSS.
13 VDDM - P Generated mid-supply, nominal 5 V.
14 VSSS - GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground.
15 VDDH - P Generated high supply, nominal 15.8 V.
16 VDRV O - Active high driver output.
GUID-20210913-SS0I-1JCS-2HZV-GDX7QXGR6LDV-low.svg Figure 5-4 TPSI313x DVX Package, 16-Pin SSOP(Top View)
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I - Active high driver enable. Internal 500 kΩ pull-down to VSSP.
2 CE I - Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500 kΩ pull-down to VSSP.
3 VSSP - GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground.
4 VDDP - P Power supply for the primary side.
5 PGOOD O - Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
6 FLT1 O - Fault 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
7 ALM1 O - Alarm 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used.
8 VSSP - GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground.
9 VSSS - GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.
10 RESP O - Used in conjunction with an external resistor connected to VSSS to adjust comparator response time. When not being used, tie to VSSS.
11 ALM1_CMP I - Analog comparator input. When ALM1_CMP voltage exceeds internal reference voltage, ALM1 is asserted low within tALM_LATENCY. Internal 3 MΩ pull-down to VSSS. When not being used, tie to VSSS.
12 FLT1_CMP I/O - Analog comparator input/output. When EN state is low, FLT1_CMP is actively pulled low. If EN state is high and FLT1_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low and FLT1 asserted low within tFLT_LATENCY. Internal 3 MΩ pull-down to VSSS. When not being used, tie to VSSS.
13 VDDM - P Generated mid-supply, nominal 5 V.
14 VSSS - GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground.
15 VDDH - P Generated high supply, nominal 15.8 V.
16 VDRV O - Active high driver output.