JAJSG04A August   2018  – June 2021 TPSM831D31

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  References: DAC
    7. 6.7  Telemetry
    8. 6.8  Current Sense and Calibration
    9. 6.9  Logic Interface Pins: A_EN, A_PGOOD, B_EN, B_PGOOD,RESET
    10. 6.10 Protections: OVP and UVP
    11. 6.11 Typical Characteristics (VIN = 12 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DCAP+ Control
      2. 7.3.2 Setting the Load-Line (DROOP)
      3. 7.3.3 Start-Up Timing
      4. 7.3.4 Load Transitions
      5. 7.3.5 Switching Frequency
      6. 7.3.6 RESET Function
      7. 7.3.7 VID Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Operation With EN Signal Control
      3. 7.4.3 Operation With OPERATION Control
      4. 7.4.4 Operation With EN and OPERATION Control
    5. 7.5 Programming
      1. 7.5.1  PMBus Connections
      2. 7.5.2  PMBus Address Selection
      3. 7.5.3  Supported Commands
      4. 7.5.4  Commonly Used PMBus Commands
      5. 7.5.5  Voltage, Current, Power, and Temperature Readings
        1. 7.5.5.1 (88h) READ_VIN
        2. 7.5.5.2 (89h) READ_IIN
        3. 7.5.5.3 (8Bh) READ_VOUT
        4. 7.5.5.4 (8Ch) READ_IOUT
        5. 7.5.5.5 (8Dh) READ_TEMPERATURE_1
        6. 7.5.5.6 (96h) READ_POUT
        7. 7.5.5.7 (97h) READ_PIN
        8. 7.5.5.8 (D4h) MFR_SPECIFIC_04
      6. 7.5.6  Output Current Sense and Calibration
        1. 7.5.6.1 Reading Individual Phase Currents
          1. 7.5.6.1.1 Reading Total Current
          2. 7.5.6.1.2 51
      7. 7.5.7  Output Voltage Margin Testing
        1. 7.5.7.1 (01h) OPERATION
        2. 7.5.7.2 (26h) VOUT_MARGIN_LOW
        3. 7.5.7.3 (25h) VOUT_MARGIN_HIGH
      8. 7.5.8  Loop Compensation
        1. 7.5.8.1 (D7h) MFR_SPECIFIC_07
        2. 7.5.8.2 (28h) VOUT_DROOP
      9. 7.5.9  Converter Protection and Response
      10. 7.5.10 Output Overvoltage Protection and Response
        1. 7.5.10.1 (40h) VOUT_OV_FAULT_LIMIT
        2. 7.5.10.2 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.5.11 Maximum Allowed Output Voltage Setting
        1. 7.5.11.1 (24h) VOUT_MAX
      12. 7.5.12 Output Undervoltage Protection and Response
        1. 7.5.12.1 (44h) VOUT_UV_FAULT_LIMIT
        2. 7.5.12.2 (45h) VOUT_UV_FAULT_RESPONSE
      13. 7.5.13 Minimum Allowed Output Voltage Setting
        1. 7.5.13.1 (2Bh) VOUT_MIN
      14. 7.5.14 Output Overcurrent Protection and Response
        1. 7.5.14.1 (46h) IOUT_OC_FAULT_LIMIT
        2. 7.5.14.2 (4Ah) IOUT_OC_WARN_LIMIT
        3. 7.5.14.3 (47h) IOUT_OC_FAULT_RESPONSE
        4. 7.5.14.4 Per Phase Overcurrent Limit Thresholds
      15. 7.5.15 Input Under-Voltage Lockout (UVLO)
        1. 7.5.15.1 (35h) VIN_ON
      16. 7.5.16 Input Over-Voltage Protection and Response
        1. 7.5.16.1 (55h) VIN_OV_FAULT_LIMIT
        2. 7.5.16.2 (56h) VIN_OV_FAULT_RESPONSE
      17. 7.5.17 Input Undervoltage Protection and Response
        1. 7.5.17.1 (59h) VIN_UV_FAULT_LIMIT
        2. 7.5.17.2 (5Ah) VIN_UV_FAULT_RESPONSE
      18. 7.5.18 Input Overcurrent Protection and Response
        1. 7.5.18.1 (5Bh) IIN_OC_FAULT_LIMIT
        2. 7.5.18.2 (5Dh) IIN_OC_WARN_LIMIT
        3. 7.5.18.3 (5Ch) IIN_OC_FAULT_RESPONSE
      19. 7.5.19 Overtemperature Protection and Response
        1. 7.5.19.1 (4Fh) OT_FAULT_LIMIT
        2. 7.5.19.2 (51h) OT_WARN_LIMIT
        3. 7.5.19.3 (50h) OT_FAULT_RESPONSE
      20. 7.5.20 Dynamic Phase Shedding (DPS)
        1. 7.5.20.1 (DEh) MFR_SPECIFIC_14
        2. 7.5.20.2 (DFh) MFR_SPECIFIC_15
      21. 7.5.21 NVM Programming
      22. 7.5.22 NVM Security
        1. 7.5.22.1 (FAh) MFR_SPECIFIC_42
      23. 7.5.23 Black Box Recording
        1. 7.5.23.1 (D8h) MFR_SPECIFIC_08
      24. 7.5.24 Board Identification and Inventory Tracking
      25. 7.5.25 Status Reporting
        1. 7.5.25.1 (78h) STATUS_BYTE
        2. 7.5.25.2 (79h) STATUS_WORD
        3. 7.5.25.3 (7Ah) STATUS_VOUT
        4. 7.5.25.4 (7Bh) STATUS_IOUT
        5. 7.5.25.5 (7Ch) STATUS_INPUT
        6. 7.5.25.6 (7Dh) STATUS_TEMPERATURE
        7. 7.5.25.7 (7Eh) STATUS_CML
        8. 7.5.25.8 (80h) STATUS_MFR_SPECIFIC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitors
        2. 8.2.2.2 Output Capacitors
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Set PMBus Address
        5. 8.2.2.5 PMBus GUI Default Values
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • MOA|28
サーマルパッド・メカニカル・データ
発注情報

7.5.25.2 (79h) STATUS_WORD

The STATUS_WORD command returns two bytes of information with a summary of critical faults, such as over-voltage, overcurrent, and over-temperature.

The STATUS_WORD command must be accessed through Read Word transactions. STATUS_WORD is a paged register. In order to access STATUS_WORD command for channel A, PAGE must be set to 00h. In order to access STATUS_WORD register for channel B, PAGE must be set to 01h. If PAGE is set FFh, the device return value will reflect the status of Channel A.

Figure 7-5 STATUS_WORD
15 14 13 12 11 10 9 8
R R R R R R R R
VOUT IOUT INPUT MFR PGOOD FANS OTHER UNKNOWN
7 6 5 4 3 2 1 0
R R R R R R R R
BUSY OFF VOUT_OV IOUT_OC VIN_UV TEMP CML OTHER
Table 7-63 STATUS_WORD Register Field Descriptions
BitFieldTypeResetDescription
15VOUTRCurrent
Status		Output Voltage Fault/Warning. Refer to STATUS_VOUT for more information.
0: Latched flag indicating no VOUT fault or warning has occurred.
1: Latched flag indicating a VOUT fault or warning has occurred.
14IOUTRCurrent
Status		Output Current Fault/Warning. Refer to STATUS_IOUT for more information.
0: Latched flag indicating no IOUT fault or warning has occurred.
1: Latched flag indicating an IOUT fault or warning has occurred.
13INPUTRCurrent
Status		Input Voltage/Current Fault/Warning. Refer to STATUS_INPUT for more information.
0: Latched flag indicating no VIN or IIN fault or warning has occurred.
1: Latched flag indicating a VIN or IIN fault or warning has occurred.
12MFRRCurrent
Status		MFR_SPECIFIC Fault. Refer to STATUS_MFR for more information.
0: Latched flag indicating no MFR_SPECIFIC fault has occurred.
1: Latched flag indicating a MFR_SPECIFIC fault has occurred.
11PGOODRCurrent
Status		Power Good Status. Note: Per the PMBus specification, the PGOOD bit is not latched, always reflecting the current status of the AVR_RDY/BVR_RDY pin.
0: Raw status indicating AVR_RDY/BVR_RDY pin is at logic high.
1: Raw status indicating AVR_RDY/BVR_RDY pin is at logic low.
10FANSR0Not supported and always set to 0.
9OTHERR0Not supported and always set to 0.
8UNKNOWNR0Not supported and always set to 0.
7BUSYR0Not supported and always set to 0.
6OFFRCurrent
Status		This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled.
0: Raw status indicating the IC is providing power to VOUT.
1: Raw status indicating the IC is not providing power to VOUT.
5VOUT_OVRCurrent
Status		Output Over-Voltage Fault Condition
0: Latched flag indicating no VOUT OV fault has occurred.
1: Latched flag indicating a VOUT OV fault occurred
4IOUT_OCRCurrent
Status		Output Over-Current Fault Condition
0: Latched flag indicating no IOUT OC fault has occurred.
1: Latched flag indicating an IOUT OC fault has occurred.
3VIN_UVRCurrent
Status		Input Under-Voltage Fault Condition
0: Latched flag indicating VIN is above the UVLO threshold.
1: Latched flag indicating VIN is below the UVLO threshold.
2TEMPRCurrent
Status		Over-Temperature Fault/Warning
0: Latched flag indicating no OT fault or warning has occurred.
1: Latched flag indicating an OT fault or warning has occurred.
1CMLRCurrent
Status		Communications, Memory or Logic Fault
0: Latched flag indicating no communication, memory, or logic fault has occurred.
1: Latched flag indicating a communication, memory, or logic fault has occurred.
0OTHERRCurrent
Status		Other Fault (None of the Above)
This bit is used to flag faults not covered with the other bit faults. In this case, UVF or OCW faults are examples of other faults not covered by the bits [7:1] in this register.
0: No fault has occurred
1: A fault or warning not listed in bits [7:1] has occurred.

Per the description in the PMBus 1.3 specification, part II, TPSM831D31 does support clearing of status bits by writing to STATUS registers. However, the bits in the STATUS_WORD are summary bits only and reflect the status of corresponding bits in STATUS_VOUT and STATUS_IOUT. To clear these bits individually, the user must clear them by writing to the corresponding STATUS_X register. For example: the output overcurrent fault sets the IOUT_OC bit in STATUS_WORD, and the IOUT_OC_FLT bit in STATUS_IOUT. Writing a 1 to the IOUT_OC_FLT bit in STATUS_IOUT clears the fault in both STATUS_WORD and STATUS_IOUT. Writes to STATUS_WORD will be treated as invalid transactions.