JAJSKD0 December   2023 TRF1305B2

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - TRF1305B2
    6. 6.6 Typical Characteristics - TRF1305B2
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Differential Amplifier
      2. 7.3.2 Output Common-Mode Control
      3. 7.3.3 Internal Resistor Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
        1. 7.4.1.1 Input Common-Mode Extension
      2. 7.4.2 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Interface Considerations
        1. 8.1.1.1 Single-Ended Input
        2. 8.1.1.2 Differential Input
        3. 8.1.1.3 DC Coupling Considerations
      2. 8.1.2 Gain Adjustment With External Resistors in a Differential Input Configuration
    2. 8.2 Typical Application
      1. 8.2.1 TRF1305x2 as ADC Driver in a Zero-IF Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Supply Voltages
      2. 8.3.2 Single-Supply Operation
      3. 8.3.3 Split-Supply Operation
      4. 8.3.4 Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 RYP Package (Dual-Channel), 16-Pin WQFN-FCRLF (Top View)
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
INM11INegative side of differential input signal for Channel 1 (Ch1).
INM25INegative side of differential input signal for Channel 2 (Ch2).
INP12IPositive side of differential input signal for Channel 1 (Ch1).
INP24IPositive side of differential input signal for Channel 2 (Ch2).
MODE7IMode selection pin. For details, see Section 7.4.1.
OUTM112ONegative side of differential output signals for Ch1.
OUTM210ONegative side of differential output signals for Ch2.
OUTP113OPositive side of differential output signals for Ch1.
OUTP29OPositive side of differential output signals for Ch2.
PD116IPower-down signal for Ch1, referenced to thermal pad. Supports both 1.8‑V and 3.3‑V logic.
Logic 0 or open = channel enabled. Logic 1 = channel powered down.
PD26IPower-down signal for Ch2, referenced to thermal pad. Supports both 1.8‑V and 3.3‑V Logic.
Logic 0 or open = channel enabled. Logic 1 = channel powered down.
REFA1, A2, A3, A4–Reference for RF signals and PD control voltage. Connect to same potential as the thermal pad.
VOCM15IOutput common-mode voltage input pin. Common for both channels. Floating the pin sets the output common-mode voltage to VS– + 2.5 V.
VS–3, 11PNegative supply pin. Common for both channels.
VS1+14PPositive supply pin for Ch1. VS1+ must be equal to VS2+.
VS2+8PPositive supply pin for Ch2. VS1+ must be equal to VS2+.
Thermal Pad17, 18, 19–PAD. Reference for RF signals and PD control voltage. Also serves as thermal pads
Connect to heat-dissipating VS– (recommended) or GND plane on the board.
(1) I = input, P = power, O = output