JAJSF39B March   2018  – June 2018 TS5USBC41

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Powered-off Protection
      2. 8.3.2 Overvoltage Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Functions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard),VCC = 2.3 V to 5.5 V, GND = 0 V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
ICC-ACTIVE Active supply current.   OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
0 V < VI/O < 3.6 V		 9 22 µA
ICC-OVP Supply current during OVP condition.  OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
VI/O > VPOS_THLD 		10 35 μA
ICC_PD Standby powered down supply current OE = 1.8 V or VCC
SEL1 = 0 V, 1.8 V, or VCC
SEL2 = 0 V, 1.8 V, or VCC		 2 6 µA
DC Characteristics
RON ON-state resistance VI/O = 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure 		5.6 9 Ω
ΔRON ON-state resistance match between channels VI/O = 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure 		0.075 0.48 Ω
RON (FLAT)  ON-state resistance flatness  VI/O = 0 V to 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure 		0.1 0.4 Ω
IOFF I/O pin OFF leakage current OE = H
VD± = 0 V or 3.6 V
VCC = 2.3 V to 5.5 V
VD1±or VD2± = 3.6 V or 0 V
Refer to Off Leakage Figure 		-4 0.1 4 µA
IOFF-20V D1/D2+/- pin OFF leakage current during OVP scenario on D+/- OE = H
VD± = 20-V
VCC = 2.3 V to 5.5 V
VD1± or VD2± = 0 V
Refer to Off Leakage Figure 		-0.5 0.5 µA
IOFF-20V-DP/N D+/- pin OFF leakage current during OVP scenario OE = H
VD± = 20-V
VCC = 2.3 V to 5.5 V
VD1± or VD2± = 0 V
Refer to Off Leakage Figure 		140 150 180 µA
IOFF-24V D1/D2 +/- pin OFF leakage current during OVP scenario on D+/-. OE = H
VD± = 24-V
VCC = 2.3 V to 5.5 V
VD1± or VD2± = 0 V
Refer to Off Leakage Figure 		-0.5 0.5 µA
IOFF-24V-DPN D+/- pin OFF leakage current during OVP scenario. OE = H
VD± = 0 V or 24-V
VCC = 2.3 V to 5.5 V
VD1± or VD2± = 0 V
Refer to Off Leakage Figure 		220 250 270 µA
ION ON leakage current. VD± = 0 V or 3.6 V
VD1± and VD2+/- = high-Z
Refer to On Leakage Figure 		-5.5 0.25 7.5 µA
Digital Characteristics
VIH Input logic high SEL1, SEL2, OE 1.4 V
VIL Input logic low SEL1, SEL2, OE 0.5 V
VOL Output logic low FLT
IOL = 3 mA		 0.4 V
IIH Input high leakage current SEL1, SEL2, OE = 1.8 V, VCC -1 1 5 μA
IIL Input low leakage current SEL1, SEL2, OE = 0 V -1 ±0.2 5 μA
RPD Internal pull-down resistor on digital input pins 6 MΩ
CI Digital input capacitance SEL1, SEL2 = 0 V, 1.8 V or VCC
f = 1 MHz		 4 pF
Protection
VOVP_TH OVP positive threshold 4.4 4.8 5.2 V
VOVP_HYST OVP threshold hysteresis 125 250 440 mV
VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario
(TS5USBC412, TS5USBC412I)		 VD± = 0 to 24 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = Open
Switch on or off
OE = 0 V		 11.2 V
VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario
(TS5USBC412, TS5USBC412I)		 VD± = 0 to 24 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = 50Ω
Switch on or off
OE = 0 V		 10.8 V
VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario
(TS5USBC410, TS5USBC410I)		 VD± = 0 to 20 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = Open
Switch on or off
OE = 0 V		 10.8 V
VCLAMP_V Maximum voltage to appear on D1± and D2± pins during OVP scenario
(TS5USBC410, TS5USBC410I)		 VD± = 0 to 20 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = 50Ω
Switch on or off
OE = 0 V		 9.8 V
VCLAMP_T Maximum OVP transient duration above 5 V (TS5USBC412, TS5USBC412I).    VD± = 0 to 24 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = Open CL = 10pF
Switch on or off
OE = 0 V		 75 100 ns
VCLAMP_T Maximum OVP transient duration above 5 V
(TS5USBC412, TS5USBC412I)		 VD± = 0 to 24 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = 50Ω CL = 10pF
Switch on or off
OE = 0 V		 68 95 ns
VCLAMP_T Maximum OVP transient duration above 5 V
(TS5USBC410, TS5USBC410I)		 VD± = 0 to 20 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = Open CL = 10pF
Switch on or off
OE = 0 V		 64 100 ns
VCLAMP_T Maximum OVP transient duration above 5 V
(TS5USBC410, TS5USBC410I)		 VD± = 0 to 20 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = 50Ω CL = 10pF
Switch on or off
OE = 0 V		 55 95 ns
tEN_OVP OVP enable time RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure 		3 μs
tREC_OVP OVP recovery time RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure 		5 μs