JAJSF24B March   2018  – October 2023 TUSB1002A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Control Inputs
      2. 7.3.2 Linear Equalization
      3. 7.3.3 Adjustable VOD Linear Range and DC Gain
      4. 7.3.4 USB3.2 Dual Channel Operation (MODE = “F”)
      5. 7.3.5 USB3.2 Single Channel Operation (MODE = “1”)
      6. 7.3.6 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
      7. 7.3.7 Basic Redriver Operation (MODE = “0”)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Disconnect Mode
    5. 7.5 U0 Mode
    6. 7.6 U1 Mode
    7. 7.7 U2/U3 Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical USB3.2 Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 ESD Protection
      4. 8.2.4 Application Curves
    3. 8.3 Typical SATA, PCIe and SATA Express Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

over operating free-air temperature and voltage range (unless otherwise noted)
MINNOMMAXUNIT
td_pgInternal power good asserted high when VCC is at 2.5V5µs
tCFG_SUCFG(1) pins setup before internal Reset(2) high0µs
tCFG_HDCFG(1) pins hold after internal Reset(2) high500µs
tVCC_RAMPVCC supply ramp requirement0.150ms
(1) Following pins comprise CFG pins:  MODE, CFG[2:1], CH1_EQ[2:1], CH2_EQ[2:1]
(2) Internal reset is the logical AND of EN pin and internal power good.