SLLSEL4A September   2014  – October 2014 TUSB1210-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Analog I/O Electrical Characteristics
    6. 6.6  Digital I/O Electrical Characteristics
    7. 6.7  Digital IO Pins (Non-ULPI)
    8. 6.8  PHY Electrical Characteristics
    9. 6.9  Pullup/Pulldown Resistors
    10. 6.10 OTG Electrical Characteristics
    11. 6.11 Power Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Timing Requirements
      1. 6.13.1 Timing Parameter Definitions
      2. 6.13.2 Interface Target Frequencies
    14. 6.14 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Processor Subsystem
        1. 7.3.1.1 Clock Specifications
          1. 7.3.1.1.1 USB PLL Reference Clock
          2. 7.3.1.1.2 ULPI Input Clock Configuration
          3. 7.3.1.1.3 ULPI Output Clock Configuration
          4. 7.3.1.1.4 Clock 32 kHz
          5. 7.3.1.1.5 Reset
        2. 7.3.1.2 USB Transceiver
          1. 7.3.1.2.1 PHY Electrical Characteristics
            1. 7.3.1.2.1.1 LS/FS Single-Ended Receivers
            2. 7.3.1.2.1.2 LS/FS Differential Receiver
            3. 7.3.1.2.1.3 LS/FS Transmitter
            4. 7.3.1.2.1.4 HS Differential Receiver
            5. 7.3.1.2.1.5 HS Differential Transmitter
            6. 7.3.1.2.1.6 UART Transceiver
          2. 7.3.1.2.2 OTG Characteristics
    4. 7.4 Device Functional Modes
      1. 7.4.1 TUSB1210-Q1 Modes vs ULPI Pin Status
    5. 7.5 Register Map
      1. 7.5.1  VENDOR_ID_LO
      2. 7.5.2  VENDOR_ID_HI
      3. 7.5.3  PRODUCT_ID_LO
      4. 7.5.4  PRODUCT_ID_HI
      5. 7.5.5  FUNC_CTRL
      6. 7.5.6  FUNC_CTRL_SET
      7. 7.5.7  FUNC_CTRL_CLR
      8. 7.5.8  IFC_CTRL
      9. 7.5.9  IFC_CTRL_SET
      10. 7.5.10 IFC_CTRL_CLR
      11. 7.5.11 OTG_CTRL
      12. 7.5.12 OTG_CTRL_SET
      13. 7.5.13 OTG_CTRL_CLR
      14. 7.5.14 USB_INT_EN_RISE
      15. 7.5.15 USB_INT_EN_RISE_SET
      16. 7.5.16 USB_INT_EN_RISE_CLR
      17. 7.5.17 USB_INT_EN_FALL
      18. 7.5.18 USB_INT_EN_FALL_SET
      19. 7.5.19 USB_INT_EN_FALL_CLR
      20. 7.5.20 USB_INT_STS
      21. 7.5.21 USB_INT_LATCH
      22. 7.5.22 DEBUG
      23. 7.5.23 SCRATCH_REG
      24. 7.5.24 SCRATCH_REG_SET
      25. 7.5.25 SCRATCH_REG_CLR
      26. 7.5.26 VENDOR_SPECIFIC1
      27. 7.5.27 VENDOR_SPECIFIC1_SET
      28. 7.5.28 VENDOR_SPECIFIC1_CLR
      29. 7.5.29 VENDOR_SPECIFIC2
      30. 7.5.30 VENDOR_SPECIFIC2_SET
      31. 7.5.31 VENDOR_SPECIFIC2_CLR
      32. 7.5.32 VENDOR_SPECIFIC1_STS
      33. 7.5.33 VENDOR_SPECIFIC1_LATCH
      34. 7.5.34 VENDOR_SPECIFIC3
      35. 7.5.35 VENDOR_SPECIFIC3_SET
      36. 7.5.36 VENDOR_SPECIFIC3_CLR
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Host or OTG, ULPI Input Clock Mode Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Unused Pins Connection
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Device, ULPI Output Clock Mode Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Unused Pins Connection
        3. 8.2.2.3 Application Curve
    3. 8.3 External Components
  9. 9 Power Supply Recommendations
    1. 9.1 TUSB1210 Power Supply
    2. 9.2 Ground
    3. 9.3 Power Providers
    4. 9.4 Power Modules
      1. 9.4.1 VDD33 Regulator
      2. 9.4.2 VDD18 Supply
      3. 9.4.3 VDD15 Regulator
    5. 9.5 Power Consumption
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
      1. 11.5.1 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Via Channel
    2. 12.2 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

Figure 5 shows the suggested application diagram (Host or OTG, ULPI input-clock mode).

8.2 Typical Application

8.2.1 Host or OTG, ULPI Input Clock Mode Application

Figure 5 shows a suggested application diagram for TUSB1210-Q1 in the case of ULPI input-clock mode (60 MHz ULPI clock is provided by link processor), in Host or OTG application. Note this is just one example, it is of course possible to operate as HOST or OTG while also in ULPI output-clock mode.

App_diagram_sllsel4.gif
A. Pin 11 (CS) : can be tied high to VIO if CS_OUT pin unavailable; Pin 14 (CFG) : tie-high is Don’t Care since ULPI clock is used in input mode
B. Pin 1 (REFCLK) : must be tied low
C. Ext 3 V supply supported
D. Pin 27 (RESETB) can be tied to VDDIO if unused.
E. Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 5. Host or OTG, ULPI Input Clock Mode Application Diagram

8.2.1.1 Design Requirements

Table 9. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VBAT 3.3 V
VDDIO 1.8 V
VBUS 5.0 V
USB Support HS, FS, LS
USB On the Go (OTG) Yes
Clock Sources 60 MHz Clock

8.2.1.2 Detailed Design Procedure

Connect the TUSB1210 device as is shown in Figure 5.

Follow the Board Guidelines of the Application Report, SWCA124.

8.2.1.2.1 Unused Pins Connection

  • VBUS: Input. Recommended to tie to GND if unused. However leaving VBUS floating is also acceptable since internally there is an 80 kΩ resistance to ground.
  • REFCLK: Input. If REFCLK is unused, and 60 MHz clock is provided by MODEM (60 MHz should be connected to CLOCK pin in this case) then tie REFCLK to GND.
  • CFG: Tie to GND if REFCLK is 19.2MHz, or tie to VDDIO if REFCLK is 26 MHz. Tie to either GND or VDDIO (doesn't matter which) if REFCLK not used (i.e., ULPI input clock configuration).

8.2.1.3 Application Curve

appcurve1_SLLSE09.gifFigure 6. High-Speed Eye Diagram

8.2.2 Device, ULPI Output Clock Mode Application

Figure 7 shows a suggested application diagram for TUSB1210-Q1 in the case of ULPI output clock mode (60 MHz ULPI clock is provided by TUSB1210-Q1, while link processor or another external circuit provides REFCLK), in Device mode application. Note this is just one example, it is of course possible to operate as Device while also in ULPI input-clock mode. Refer also to Figure 5.

App2_diagram_sllsel4.gif
A. Pin 11 (CS) : can be tied high to VIO if CS_OUT pin unavailable; Pin 14 (CFG) : Tied to VDDIO for 26MHz REFCLK mode here, tie to GND for 19.2MHz mode.
B. Pin 1 (REFCLK) : connect to external 3.3V square-wave reference clock
C. Ext 3 V supply supported
D. Pin 27 (RESETB) can be tied to VDDIO if unused.
E. Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 7. Device, ULPI Output Clock Mode Application Diagram

8.2.2.1 Design Requirements

Table 10. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VBAT 3.3 V
VDDIO 1.8 V
VBUS 5.0 V
USB Support HS, FS, LS
Clock Sources 26 MHz or 19.2 MHz Oscillator

8.2.2.2 Detailed Design Procedure

Connect the TUSB1210 device as is shown in Figure 7.

Follow the Board Guidelines of the Application Report, SWCA124.

8.2.2.2.1 Unused Pins Connection

  • ID: Input. Leave floating if unused or TUSB1210-Q1 is Device mode only. Tie to GND through RID < 1 kOhm if Host mode.
  • REFCLK: Input. If REFCLK is unused, and 60 MHz clock is provided by MODEM (60 MHz should be connected to CLOCK pin in this case) then tie REFCLK to GND.
  • CFG: Tie to GND if REFCLK is 19.2MHz, or tie to VDDIO if REFCLK is 26 MHz. Tie to either GND or VDDIO (doesn't matter which) if REFCLK not used (i.e., ULPI input clock configuration).

8.2.2.3 Application Curve

appcurve2_SLLSE09.gifFigure 8. Full-Speed Eye Diagram

8.3 External Components

Table 11. TUSB1210-Q1 External Components

FUNCTION COMPONENT REFERENCE VALUE NOTE LINK
VDDIO Capacitor CVDDIO 100 nF Suggested value, application dependent Figure 5
VDD33 Capacitor CVDD33 2.2 μF Range: [0.45 μF : 6.5 μF] ,
ESR = [0 : 600 mΩ] for f> 10 kHz		 Figure 5
VDD15 Capacitor CVDD15 2.2 μF Range: [0.45 μF : 6.5 μF] ,
ESR = [0 : 600 mΩ] for f> 10 kHz		 Figure 5
VDD18 Capacitor Ext 1.8V supply 100 nF Suggested value, application dependent Figure 5
CVDD18
VBAT Capacitor CBYP 100 nF(1) Range: [0.45 μF : 6.5 μF] ,
ESR = [0 : 600 mΩ] for f> 10 kHz		 Figure 5
VBUS Capacitor CVBUS See Table 12 Place close to USB connector Figure 5
(1) Recommended value but 2.2 uF may be sufficient in some applications

Table 12. TUSB1210-Q1 VBUS Capacitors

FUNCTION COMPONENT REFERENCE VALUE NOTE LINK
VBUS - HOST Capacitor CVBUS >120 μF Figure 5
VBUS – DEVICE Capacitor CVBUS 4.7 μF Range: 1.0 μF to 10.0 μF Figure 5
VBUS - OTG Capacitor CVBUS 4.7 μF Range: 1.0 μF to 6.5 μF Figure 5