JAJSSZ7 February   2024 TUSB211A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Speed EQ
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low-Speed (LS) Mode
      2. 6.4.2 Full-Speed (FS) Mode
      3. 6.4.3 High-Speed (HS) Mode
      4. 6.4.4 High-Speed Downstream Port Electrical Compliance Test Mode
      5. 6.4.5 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Test Procedure to Construct USB High-Speed Eye Diagram
          1. 7.2.2.1.1 For a Host Side Application
          2. 7.2.2.1.2 For a Device Side Application
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RWB|12
サーマルパッド・メカニカル・データ
発注情報

5.7 Timing Requirements

MIN NOM MAX UNIT
POWER UP TIMING
TRSTN_PW Minimum width to detect a valid RSTN signal assert when the pin is actively driven low 100 µs
TSTABLE VCC must be stable before RSTN de-assertion 300 µs
TREADY Maximum time needed for the device to be ready after RSTN is de-asserted. 500 µs
TRAMP VCC ramp time 100 ms
TRAMP VCC ramp time 0.2 ms