JAJSCK3E July   2016  – November 2023 TUSB522P

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, Power Supply
    6. 6.6 Electrical Characteristics, DC
    7. 6.7 Electrical Characteristics, AC
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Receiver Equalization
      2. 7.3.2 De-Emphasis Control and Output Swing
      3. 7.3.3 Automatic LFPS Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration
      2. 7.4.2 Power Modes
        1. 7.4.2.1 U0 Mode (Active Power Mode)
        2. 7.4.2.2 U2/U3 (Low Power Mode)
        3. 7.4.2.3 Disconnect Mode - RX Detect
        4. 7.4.2.4 Shutdown Mode
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

  • RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).
  • Keep away from other high speed signals.
  • Intra-pair routing should be kept to within 2mils.
  • Length matching should be near the location of mismatch.
  • Each pair should be separated at least by 3 times the signal trace width.
  • The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
  • Route all differential pairs on the same of layer.
  • The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
  • Keep traces on layers adjacent to ground plane.
  • Do not route differential pairs over any plane split.
  • Adding test points will cause impedance discontinuity; and will therefore, negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.
  • The 100-nF capacitors on the TXP and SSTXN nets must be placed close to the USB connector (Type A, Type B, and so forth).
  • The ESD and EMI protection devices (if used) must also be placed as close as possible to the USB connector.
  • Place voltage regulators as far away as possible from the differential pairs.
  • To minimize crosstalk, TI recommends keeping high-speed signals away from each other. Each pair must be separated by at least 5 times the signal trace width. Separating with ground also helps minimize crosstalk.