JAJSQH5E November   2013  – October 2023 TXS0104E-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements—VCCA = 1.8 V ± 0.15 V
    7. 6.7  Timing Requirements—VCCA = 2.5 V ± 0.2 V
    8. 6.8  Timing Requirements—VCCA = 3.3 V ± 0.3 V
    9. 6.9  Switching Characteristics—VCCA = 1.8 V ± 0.15 V
    10. 6.10 Switching Characteristics—VCCA = 2.5 V ± 0.2 V
    11. 6.11 Switching Characteristics—VCCA = 3.3 V ± 0.3 V
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Load Circuits
    2. 7.2 Voltage Waveforms
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Architecture
      2. 8.3.2 Input Driver Requirements
      3. 8.3.3 Power Up
      4. 8.3.4 Enable and Disable
      5. 8.3.5 Pull Up and Pull Down Resistors on I/O Lines
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
  12. 11静電気放電に関する注意事項
  13. 12用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RUT|12
  • PW|14
  • BQA|14
サーマルパッド・メカニカル・データ
発注情報

8.3.1 Architecture

The TXS0104E-Q1 architecture (see Figure 8-1) does not require a direction-control signal in order to control the direction of data flow from A to B or from B to A.

GUID-101857BB-13C7-44DE-ADA7-AE8BF79A1703-low.gifFigure 8-1 Architecture of a TXS01xx Cell

Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup resistor to VCCB. The output one-shots detect rising edges on the A or B ports. During a rising edge, the one-shot turns on the PMOS transistors (T1, T2) for a short duration which speeds up the low-to-high transition.