JAJSK71X january   1976  – june 2023 UA78L

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: UA78L02 (Legacy Chip Only)
    6. 6.6  Electrical Characteristics: UA78L033 (New Chip Only)
    7. 6.7  Electrical Characteristics: UA78L05 (Both Legacy and New Chip)
    8. 6.8  Electrical Characteristics: UA78L12 (Both Legacy and New Chip)
    9. 6.9  Electrical Characteristics: UA78L06 (Legacy Chip Only)
    10. 6.10 Electrical Characteristics: UA78L08 (Legacy Chip Only)
    11. 6.11 Electrical Characteristics: UA78L09 (Legacy Chip Only)
    12. 6.12 Electrical Characteristics: UA78L10 (Legacy Chip Only)
    13. 6.13 Electrical Characteristics: UA78L15 (Both Legacy and New Chip)
    14. 6.14 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Thermal Shutdown
      3. 7.3.3 Dropout Voltage (VDO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Power Dissipation (PD)
        3. 8.2.2.3 Estimating Junction Temperature
        4. 8.2.2.4 External Capacitor Requirements
        5. 8.2.2.5 Overload Recovery
        6. 8.2.2.6 Reverse Current
        7. 8.2.2.7 Polarity Reversal Protection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Positive Regulator in Negative Configuration
      2. 8.3.2 Current Limiter Circuit
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • PK|3
  • LP|3
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-7B08A771-3208-445C-A749-71599FE5ECAC-low.svgFigure 5-1 D Package,8-Pin SOIC(Top View)
GUID-7867657E-99BD-4029-95CC-89C8B997D442-low.gifFigure 5-3 PK Package,3-Pin SOT-89(Top View)
GUID-58980066-3F2A-46D1-904A-EBF2DAA52A63-low.gifFigure 5-2 LP Package,3-Pin TO-92(Top View)
PIN TYPE DESCRIPTION
NAME SOIC TO-92 SOT-89
COMMON 2, 3, 6, 7 2 2 — Ground
INPUT 8 3 3 I Input pin. Use the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the device as possible.
OUTPUT 1 1 1 O Output pin. Use the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the output capacitor as close to the OUT and GND pins of the device as possible.
NC 4, 5 — — — No connect pin. This pin is not connected internally. Connect this pin to ground for best thermal performance or leave floating.