JAJSHX9D september   2019  – january 2021 UCC12050

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーションと実装
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 UVLO, Power-Up, and Power-Down Behavior
      3. 7.3.3 VISO Load Recommended Operating Area
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 External Clocking and Synchronization
      6. 7.3.6 VISO Output Voltage Selection
      7. 7.3.7 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VISO Output Capacitor Selection
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical and Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics

Over operating temperature range (TJ = –40°C to 150°C), VINP = 4.5V to 5.5V, CINP = COUT = 10 µF, SEL connected to VISO, internal clock mode, unless otherwise noted. All typical values at TJ = 25°C and VINP = 5.0V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY
IVINQVINP quiescent current,disabledEN=LOW100uA
IVINOVINP operating current, no loadEN=HI; SEL shorted to VISO (5.0V output)50mA
EN=HI; SEL 100kΩ to VISO (5.4V output) 45 
EN=HI; SEL shorted to GNDS (3.3V output)90
EN=HI; SEL 100kΩ to GNDS (3.7V output) 80 
IVIN_SCDC current from VINP supplyunder short circuit on VISOVISO short to GNDS245mA
VUVPRVINP under-voltage lockout rising threshold4.2V
VUVPFVINP under-voltage lockout falling threshold3.7V
VUVPHVINP under-voltage lockout hysteresis0.5V
EN, SYNC INPUT PINS
VIRInput voltage threshold, logic HIGHRising edge2.2V
VIFInput voltage threshold, logic LOWFalling edge0.8V
IENEnable Pin Input CurrentVEN = 5.0 V510uA
ISYNCSYNC Pin Input CurrentVSYNC = 5.0 V0.021uA
SYNC_OK PIN
VOLSYNC_OK output low voltageISYNC_OK = - 2 mA0.15V
ILKG_SYNC_OKSYNC_OK pin leakage currentVSYNC_OK = 5.0 V1uA
DC/DC CONVERTER
VISOIsolated supply output voltageSEL shorted to VISO (5.0V output); IISO = 55 mA (2)4.755.3V
SEL 100kΩ to VISO (5.4 V output); IISO = 45 mA (2)5.15.45.7V
SEL shorted to GNDS (3.3V output); IISO = 100 mA (2)3.13.33.5V
SEL 100kΩ to GNDS (3.7 V output); IISO = 90 mA (2)3.53.73.9V
VISO(RIP)Voltage ripple on isolated supply output (pk-pk)20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF, SEL shorted to VISO (5.0V output); IISO = 100 mA50mV
20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF, SEL 100kΩ to VISO (5.4V output); IISO = 90 mA50mV
20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF, SEL shorted to GNDS (3.3V output); IISO = 145 mA50mV
20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF, SEL shorted to GNDS (3.7V output); IISO = 130 mA50mV
VISO(LINE)VISO DC line regulationSEL shorted to VISO (5.0 V output); IISO = 50 mA, VINP = 4.5 V to 5.5 V1%
SEL shorted to GNDS (3.3 V output); IISO = 75 mA, VINP = 4.5 V to 5.5 V1%
VISO(LOAD)VISO DC load regulationSEL shorted to VISO (5.0 V output); IISO = 0 to 100 mA1.5%
VISO DC load regulationSEL shorted to GNDS (3.3 V output); IISO = 0 to 145 mA1.5%
EFFEfficiency at maximum recommended load (1)SEL shorted to VISO (5.0 V output); IISO = 100 mA60%
SEL 100kΩ to VISO (5.4V output); IISO = 90 mA 60%  
SEL shorted to GNDS (3.3V output); IISO = 145 mA50%
SEL 100kΩ to GNDS (3.7V output); IISO = 130 mA 53%  
tRISEVISO rise time, 10% - 90%EN = change from LO to HI, SEL shorted to VISO (5.0V output); IISO = 1 mA750µs
EN = change from LO to HI, SEL 100kΩ to GNDS (3.3V output); IISO = 1 mA300µs
THERMAL SHUTDOWN
TSDTHRThermal shutdown threshold Junction Temperature, Rising165°C
TSDHYSTThermal shutdown hysteresis Junction Temperature, Falling27°C
(1) Efficiency calculation: EFF = (VISO x IISO) / (VINP x IINP)
(2) See the Section 7.3.3 section for discussion of VISO regulation across load and temperature conditions for all output voltage settings.