JAJSQ34A april   2023  – august 2023 UCC14131-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Electrical Characteristics
    7. 7.7 Safety Limiting Values
  9. 8 Safety-Related Certifications
  10. 9 Insulation Characteristics
  11. 10Typical Characteristics
  12. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 Functional Block Diagram
    3. 11.3 Feature Description
      1. 11.3.1 Power Stage Operation
        1. 11.3.1.1 VDD-VEE Voltage Regulation
        2. 11.3.1.2 COM-VEE Voltage Regulation
        3. 11.3.1.3 Power Handling Capability
      2. 11.3.2 Output Voltage Soft Start
      3. 11.3.3 ENA and PG
      4. 11.3.4 Protection Functions
        1. 11.3.4.1 Input Undervoltage Lockout
        2. 11.3.4.2 Input Overvoltage Lockout
        3. 11.3.4.3 Output Undervoltage Protection
        4. 11.3.4.4 Output Overvoltage Protection
        5. 11.3.4.5 Overpower Protection
        6. 11.3.4.6 Overtemperature Protection
    4. 11.4 Device Functional Modes
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1 Capacitor Selection
        2. 12.2.2.2 Single RLIM Resistor Selection
        3. 12.2.2.3 RDR Circuit Component Selection
        4. 12.2.2.4 Feedback Resistors Selection
    3. 12.3 System Examples
    4. 12.4 Power Supply Recommendations
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
  16. 15Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Electrical Characteristics

Over operating temperature range ( –40 °C ≤ TJ ≤ 150 °C), 8 V ≤ VVIN  ≤ 18 V, CIN = 20 µF, COUT = 10 µF, VENA = 5 V, RLIM = 1 kΩ unless otherwise noted. All typical values at TJ = 25 °C and VVIN = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY (Primary-side. All voltages with respect to GNDP)
VVIN Input voltage range(1) Primary-side input voltage to GNDP, 1-W output power 8 12 18 V
IVINQ_OFF VIN quiescent current, disabled VENA = 0 V; VVIN =8 V - 18 V 600 µA
IVIN_ON_NO_LOAD VIN operating current, enabled, No Load VENA = 5 V; VVIN = 8 V - 18 V; (VDD-VEE) = 12-V regulating; IVDD-VEE = 0 mA 40 mA
IVIN_ON_FULL_LOAD VIN operating current, enabled, Full Load VENA = 5 V; VVIN = 10 V - 18 V; (VDD-VEE) = 12-V regulating; IVDD-VEE = 83 mA 200 mA
IVIN_ON_FULL_LOAD VIN operating current, enabled, Full Load VENA = 5 V; VVIN = 10.8 V - 13.2 V; (VDD-VEE) = 12-V regulating; IVDD-VEE = 125 mA 270 mA
UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP)
VVIN_UVLOP_RISING VIN underv-oltage lockout rising threshold VIN rising 7.8 8.2 8.5 V
VVIN_ UVLOP_FALLING VIN under-voltage lockout falling threshold VIN falling 7 7.4 7.7 V
OVLO COMPARATOR (Primary-side. All voltages with respect to GNDP)
VVIN_OVLO_RISE VIN over-voltage lockout rising threshold VIN rising 20.9 22 23.1 V
VVIN_OVLO_FALLING VIN over-voltage lockout falling threshold VIN falling 19 20 21 V
THERMAL SHUTDOWN (Primary side)
TSHUTPPRIMARY_RISE Primary-side over-temperature shutdown rising threshold First time at power-up Tj needs to be < 140 °C to turnon 150 160 170 °C
TSHUTPPRIMARY_HYST Primary-side over-temperature shutdown hysteresis 15 20 25 °C
ENA INPUT PIN (Primary-side. All voltages with respect to GNDP)
VEN_IR Input voltage rising threshold, logic HIGH Rising edge 2.1 V
VEN_IF Input voltage falling threshold, logic LOW Falling edge 0.8 V
IEN Enable Pin Input Current VEN = 5.0 V 5 18 µA
POWERGOOD (Primary-side. All voltages with respect to GNDP) 
VPG_OUT_LO PG output-low saturation voltage Sink Current = 5 mA, power good 0.5 V
IPG_OUT_HI PG Leakage current VPG = 5.5 V, power not good 5 µA
Primary-side Control (Primary-side. All voltages with respect to GNDP)
FSW Switching frequency VVIN = 12 V; VENA = 5 V; (VDD-VEE) = 12 V 20.5 MHz
FSSM Frequency of Spread Spectrum Modulation (SSM) triangle waveform Only during primary-side startup starting after VIN > UVLOP, and EN = HIGH; FSS_BURST_P = 1/8 µs = 125 kHz 90 kHz
SSM Percentage change of FCARRIER SSM Percent change of carrier frequency during Spread Spectrum Modulation (SSM) by triangle waveform Only during primary-side startup starting after VIN > UVLOP, and EN = HIGH; FSS_BURST_P = 1/8 µs = 125 kHz 5 %
tSOFT_START_TIME_OUT Primary-side soft-start time-out Timer begins when VIN > UVLOP and ENA = High and reset when Powergood pin indicates Good 28.4 ms
VDD OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVDD_RANGE (VDD – VEE) Output voltage range 10 18 V
VVDD_DC_ACCURACY (VDD – VEE) Output
voltage DC
regulation
accuracy

 
Secondary-side (VDD – VEE) output voltage, over load, line and temperature range, externally adjust with external resistor divider
 		 -1.3 1.3 %
VDD REGULATION (Secondary-side. All voltages with respect to VEE)
VFBVDD_REF Feedback regulation reference voltage for (VDD – VEE) (VDD – VEE) output in regulation 2.4675 2.5 2.5325 V
COM OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVEE_RANGE (COM – VEE) Output voltage range Secondary-side (COM – VEE), adjust with external resistor divider 2.5 (VDD – VEE) V
VVEE_DC_ACURACY
(COM - VEE)
Output voltage DC
regulation accuracy

 
Secondary-side (COM – VEE)
output voltage, over load, line and temperature range, externally adjust with external resistor
divider		 –1.3 1.3 %
COM REGULATION (Secondary-side. All voltages with respect to VEE)
VFBVEE_REF Feedback regulation reference voltage for (COM – VEE) (COM – VEE) output in regulation 2.4675 2.5 2.5325 V
VRLIM_SHORT_CHRG _CMP_RISE RLIM Short Charge comparator rising threshold to exit PWM Rising threshold 0.73 V
tRLIM_SHORT_CHRG_ ON_TIME On-Time during RLIM pin Short Charge PWM mode RLIM pin < 0.645 V, while FBVEE pin < 2.48 V 1.2 us
tRLIM_SHORT_CHRG_ OFF_TIME Off-Time during RLIM pin Short Charge PWM mode RLIM pin < 0.645 V, while FBVEE pin < 2.48 V 5 us
VDD UVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE) 
VVDD_UVLO_RISE (VDD – VEE) undervoltage lockout rising threshold Voltage at FBVDD 0.9 V
VVDD_UVLO_HYST (VDD – VEE) undervoltage lockout hysteresis Voltage at FBVDD 0.2 V
VDD OVLOS COMPARATOR (Secondary-side. All voltages with respect to VEE)
VVDD_OVLOS_RISE (VDD – VEE) over-voltage lockout rising threshold Voltage from VDD to VEE, rising 29.45 31 32.55 V
VVDD_OVLOS_FALL (VDD – VEE) over-voltage lockout falling threshold Voltage from VDD to VEE, falling 27.55 29 30.45 V
SOFT-START (Secondary-side. All voltages with respect to VEE)
tblankout Blank out time after soft start before PG for (VDD-VEE) UVP and (COM-VEE) UVP & OVP 3 ms
(VDD – VEE) UVP,  UNDER -VOLTAGE PROTECTION (Secondary-side. All voltages with respect to VEE)
VVDD_UVP_RISE (VDD – VEE) under-voltage protection rising threshold, VUVP = VREF × 90% 2.175 2.25 2.3 V
VVDD_UVP_HYST (VDD – VEE) under-voltage protection hysteresis 25 mV
(VDD – VEE) OVP,  OVER-VOLTAGE PROTECTION  (Secondary-side. All voltages with respect to VEE)
VVDD_OVP_RISE (VDD – VEE) over-voltage protection rising threshold, VOVP = VREF ×110% 2.7 2.75 2.825 V
VVDD_OVP_HYST (VDD – VEE) over-voltage protection hysteresis 25 mV
(COM – VEE) UVP, UNDER -VOLTAGE PROTECTION  (Secondary-side. All voltages with respect to VEE)
VVEE_UVP_RISE (COM – VEE) under-voltage protection rising threshold, VUVP = VREF × 90% 2.175 2.25 2.3 V
VVEE_UVP_HYST (COM – VEE) under-voltage protection hysteresis 25 mV
(COM – VEE) OVP, OVER-VOLTAGE PROTECTION (Secondary-side. All voltages with respect to VEE)
VVEE_OVP_RISE (COM – VEE) over-voltage protection rising threshold, VOVP = VREF × 110% 2.7 2.75 2.825 V
VVEE_OVP_HYST (COM – VEE) over-voltage protection hysteresis 25 mV
THERMAL SHUTDOWN(Secondary side)
TSHUTSSECONDARY_RISE Secondary -side over-temperature shutdown rising threshold First time at power-up Tj needs to be < 140oC to turnon. 150 160 170 °C
TSHUTSSECONDARY_HYST Secondary-side over-temperature shutdown hysteresis 15 20 25 °C
CMTI (Common Mode Transient Immunity)
CMTI Common Mode Transient Immunity Positive VEE with respect to GNDP 150 V/ns
Negative VEE with respect to GNDP -150 V/ns
INTEGRATED TRANSFORMER
N Transformer effective turns ratio Secondary side to primary side 1.51 -
(1) VVIN needs to be above VVIN_UVLOP_RISING first before it operates with the minimum input voltage.