JAJSQN3 june   2023  – june 2023 UCC14140-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Insulation Specifications
    6. 7.6  Safety-Related Certifications
    7. 7.7  Electrical Characteristics
    8. 7.8  Safety Limiting Values
    9. 7.9  Insulation Characteristics
    10. 7.10 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Stage Operation
        1. 8.3.1.1 VDD-VEE Voltage Regulation
        2. 8.3.1.2 COM-VEE Voltage Regulation
        3. 8.3.1.3 Power Handling Capability
      2. 8.3.2 Output Voltage Soft Start
      3. 8.3.3 ENA and PG
      4. 8.3.4 Protection Functions
        1. 8.3.4.1 Input Undervoltage Lockout
        2. 8.3.4.2 Input Overvoltage Lockout
        3. 8.3.4.3 Output Undervoltage Protection
        4. 8.3.4.4 Output Overvoltage Protection
        5. 8.3.4.5 Overpower Protection
        6. 8.3.4.6 Overtemperature Protection
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Capacitor Selection
        2. 9.2.2.2 Single RLIM Resistor Selection
        3. 9.2.2.3 RDR Circuit Component Selection
    3. 9.3 System Examples
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Design Requirements

Designing with the UCC14140-Q1 module is simple. First, choose single output or dual output. Determine the voltage for each output and then set the regulation through resistor dividers. Second, select the recommended input and output capacitors according to the procedure in the section of capacitor selection. The gate charge of the power device determines the amount of output decoupling capacitance needed at the gate driver input. Third, calculate the RLIM resistor value for regulating the (COM – VEE) voltage rail for a dual output according to the procedure in the section of RLIM or RDR selection.

For the dual output configuration, the VDD-to-VEE output capacitor placement and the RLIM-to-COM resistance introduce great impact to the power module performance and system BOM cost. Table 9-1 compares four combinations of two different VDD-to-VEE output decoupling capacitor placements and two RLIM current-limit networks. The number 1 ranking represents the best, and the number 4 means the worst. The table indicates that case B offers the best performance and case A offers the lowest BOM cost. As shown in Figure 9-1, COUT1 is the decoupling capacitor closest to VDD and VEE pins, while COUT1B is the decoupling capacitor closest to the output load. Besides, the current-limit resistor network between RLIM pin and COM terminal is called the RDR circuitry, which can program the charge and discharge current of RLIM regulator independently.

For the gate driver application with high di/dt current change as example, the finite impedance between the output terminal of power modules and the input bias terminal of output load greatly affects the transient response at the point of load, so the local decoupling capacitor COUT1B provides a very effective low-impedance decoupling for both VVDD-to-COM and VCOM-to-VEE in the driver switching condition. From the schematic aspect, it seems that adding COUT1B means one more extra capacitor, but the reality is that it helps to avoid the need of oversizing COUT2 and COUT3. With COUT1B, the reduced capacitance and capacitor body size for COUT2 and COUT3 end up a reduced total BOM cost on output capacitor bank. The following Section 9.2.2.1 will describe the design procedure of COUT1B for more detail. Another benefit is that when capacitance of COUT2 and COUT3 is reduced, a higher RLIM resistance can be used for COM-to-VEE regulation, so the power loss of RLIM regulator is reduced for higher power module efficiency.

Table 9-1 Comparison of four design cases and their system-level implications
COUT1B

RDR

Output RippleEfficiencyExternal BOM count/cost

Case A

Yes

No

3

3

1 (Lowest)

Case B

Yes

Yes

1 (Lowest)

1 (Highest)

2

Case C

No

No

4

4

3

Case D

No

Yes

2

2

4

As shown in Figure 9-1, the RDR circuitry is a current-limit resistor network of the RLIM pin to allow RLIM regulator to optimize the charge and discharge current capabilities independently for further increasing the power module efficiency from the reduced power loss of RLIM regulator. The circuity consists of three components, one high-resistance resistor RLIM1 in parallel with another resistor-diode branch, a small-resistance resistor RLIM2 in series with a small-signal diode DLIM. RLIM1 resistance is much higher than RLIM2 resistance. Since VVDD-to-VEE is usually much higher than VCOM-to-VEE especially in gate drive application, RLIM1 provides a high-resistance path for the internal charge switch to greatly reduce the switch current, so as to reduce the switching loss and conduction loss of the internal charge switch as well as the power loss of RLIM1 for higher efficiency. In addition, with a smaller charge current, the disturbance to VVDD-to-VEE ripple dipping effect at the charge switch turn-on instance will be minimized, so the total peak-to-peak ripple is reduced.

When the discharge switch turns on, the DLIM provides a unidirectional path to divert most of the RLIM-pin current back to RLIM2. This approach allows the RLIM regulator equipped with strong enough sinking capability to avoid the unbalanced current at COM-pin terminal from charging up VCOM-to-VEE away from regulation band. Since VCOM-to-VEE is lower than VVDD-to-VEE such as -5V respect to 25V as example, the power loss of the internal discharge switch and RLIM2 with larger switching current is less concern. On the contrary, if only one resistor is used to the RLIM pin, the resistor needs to design for worst case with lowest resistance to ensure VCOM-to-VEE regulation, so the efficiency will be compromised. For example, the RDR circuitry with RLIM1 of 1kΩ and RLIM2 of 51Ω can increase the converter efficiency 7% higher with 10mA load from VDD to COM and reduce the case temperature 10°C, compared with using one RLIM of 51Ω only.

Based on above, Case B is highly recommended as first choice in application. User can still use other thee design cases for other considerations. The design calculator provides a generic calculation tool to help user optimize each. The equations are based on the below detail descriptions.