JAJSG66B November   2018  – March 2019 UCC21540 , UCC21541

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     機能ブロック図
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety-Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Thermal Derating Curves
    12. 7.12 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Minimum Pulses
    2. 8.2 Propagation Delay and Pulse Width Distortion
    3. 8.3 Rising and Falling Time
    4. 8.4 Input and Disable Response Time
    5. 8.5 Programmable Dead Time
    6. 8.6 Power-up UVLO Delay to OUTPUT
    7. 8.7 CMTI Testing
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in the UCC2154x
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 DT Pin Tied to VCCI
        2. 9.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing INA/INB Input Filter
        2. 10.2.2.2 Select Dead Time Resistor and Capacitor
        3. 10.2.2.3 Select External Bootstrap Diode and its Series Resistor
        4. 10.2.2.4 Gate Driver Output Resistor
        5. 10.2.2.5 Estimating Gate Driver Power Loss
        6. 10.2.2.6 Estimating Junction Temperature
        7. 10.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.7.1 Selecting a VCCI Capacitor
          2. 10.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.7.3 Select a VDDB Capacitor
        8. 10.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Component Placement Considerations
      2. 12.1.2 Grounding Considerations
      3. 12.1.3 High-Voltage Considerations
      4. 12.1.4 Thermal Considerations
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 関連リンク
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for gate drive current transients up to 4-A, the source peak current, and needs to maintain a stable gate drive voltage for the power transistor.

The total charge needed per switching cycle can be estimated with

Equation 19. UCC21540 UCC21541 eq19_slusck0.gif

where

  • QG: Gate charge of the power transistor.
  • IVDD: The channel self-current consumption with no load at 100kHz.

Therefore, the absolute minimum CBoot requirement is:

Equation 20. UCC21540 UCC21541 eq20_slusck0.gif

where

  • ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.

In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients. Therefore, it is recommended to include a margin in the CBoot value and place it as close to the VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

Equation 21. UCC21540 UCC21541 eq21_slusck0.gif

To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance.

NOTE

Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and VBOOT could stay below UVLO. As a result, the high-side FET does not follow input signal command. Also during initial CBOOT charging cycles, the bootstrap diode has highest reverse recovery current and losses.