JAJSC46B February   2011  – July 2015 UCC27200A , UCC27201A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stages
        1. 7.3.1.1 UVLO (Undervoltage Lockout)
        2. 7.3.1.2 Level Shift
        3. 7.3.1.3 Boot Diode
        4. 7.3.1.4 Output Stages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching the MOSFETs
        2. 8.2.2.2 Dynamic Switching of the MOSFETs
        3. 8.2.2.3 Delay Matching and Narrow Pulse Widths
        4. 8.2.2.4 Boot Diode Performance
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

To improve the switching characteristics and efficiency of a design, the following layout rules should be followed.

  • Locate the driver as close as possible to the MOSFETs.
  • Locate the VDD and VHB (bootstrap) capacitors as close as possible to the driver.
  • Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFET but should not be in the high current path of the MOSFET(S) drain or source current.
  • Use similar rules for the HS node as for GND for the high side driver.
  • Use wide traces for LO and HO closely following the associated GND or HS traces. 60 mil to 100 mil width is preferable where possible.
  • Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another. For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic inductance.
  • Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads.
  • Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can even lead to decreased reliability of the whole system.

These references and links to additional information may be found at www.ti.com.

  1. Additional layout guidelines for PCB land patterns may be found in Application Brief SLUA271
  2. Additional thermal performance guidelines may be found in Application Reports SLMA002 and SLMA004

10.2 Layout Example

UCC27200A UCC27201A fig35_lus746.gif Figure 36. Example Component Placement