JAJSC56F December   2012  – March 2018 UCC27611

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Undervoltage Lockout
      2. 7.3.2 Operating Supply Current
      3. 7.3.3 Input Stage
      4. 7.3.4 Enable Function
      5. 7.3.5 Output Stage
      6. 7.3.6 Low Propagation Delays
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Supply Voltage
        2. 8.2.2.2 Input Configuration
        3. 8.2.2.3 Output Configuration
        4. 8.2.2.4 Power Dissipation
        5. 8.2.2.5 Thermal Considerations
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1 Design Requirements

The requirements of gate-driver for driving enhancement mode GaN FET are listed as below:

  • The headroom between the recommended gate-drive voltage and the absolute maximum rating of GaN transistor is generally marginal. It is critical to drive the GaN FET by an accurate gate-drive supply voltage
  • The turnon threshold of the GaN transistor is generally much lower than that of silicon MOSFETs, the risk of Miller turnon and shoot-through becomes a concern for the higher-voltage devices. Low pulldown impedance is necessary to boost the immunity of Miller turnon
  • With enhancement mode GaN transistors, the need for minimizing pulldown impedance means that addition pulldown gate resistor and antiparallel diode connection is not recommended. Split the gate pullup and pulldown connections and allow the insertion of external pullup resistance for EMI and voltage-overshoot control is needed
  • At high switching speeds, the impact of the gate-drive interconnection impedance becomes important, low-inductance packages with good thermal capability is required for gate driver