JAJSC44B August   2015  – March 2017 UCC27714

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Under Voltage Lockout
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Level Shift
      6. 7.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 7.3.7 Parasitic Diode Structure in UCC27714
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Function
      2. 7.4.2 Minimum Input Pulse Operation
      3. 7.4.3 Operation with HO and LO Outputs High Simultaneously
      4. 7.4.4 Operation Under 100% Duty Cycle Condition
      5. 7.4.5 Operation Under Negative HS Voltage Condition
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 8.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 8.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 8.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 8.2.2.5 Selecting Gate Resistor RHO/RLO
        6. 8.2.2.6 Selecting Bootstrap Diode
        7. 8.2.2.7 Estimate the UCC27714 Power Losses (PUCC27714)
        8. 8.2.2.8 Application Example Schematic Note
        9. 8.2.2.9 LO and HO Overshoot and Undershoot
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
    5. 11.5 ドキュメントの更新通知を受け取る方法
    6. 11.6 コミュニティ・リソース
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1) (2)

Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to COM (unless otherwise noted), currents are positive into and negative out of the specified terminal. (1)
MIN MAX UNIT
VIN Input voltage range HI, LI, EN(3) with respect to VSS –5 20 V
VDD supply voltage –0.3 20 V
HB –0.3 640 V
HB-HS –0.3 20 V
VOUT Output voltage range, HO DC HS – 0.3 HB + 0.3 V
Transient, less than 100 ns(4) HS – 2 HB + 0.3 V
Output voltage range, LO DC –0.3 VDD + 0.3 V
Transient, less than 100 ns(4) –2 VDD + 0.3 V
Logic ground, With respect to COM –7 6 V
Logic ground, VDD-VSS –0.3 20 V
IOUT Output current, HO, LO, IOUT_PULSED (100 ns) ±4 A
IOUT Output current, HO, LO, IOUT_DC 0.25 A
dVHS/dt Allowable offset supply voltage transient –50 50 V/ns
Lead temperature (soldering, 10 second) 300 °C
TJ Junction temperature range –40 150 °C
Tstg Storage temperature range -65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3) The maximum voltage on the Input pins is not restricted by the voltage on the VDD pin.
(4) Values are verified by characterization on bench.

6.2 ESD Ratings

VALUE UNIT
V(ESD)(1) Electrostatic discharge Human body model, HBM ±1400 V
Charge device model, CDM ±500 V
(1) These devices are sensitive to electrostatic discharge; follow proper device handing procedures

6.3 Recommended Operating Conditions

All voltages are with respect to COM, –40°C < TJ < 125°C, currents are positive into, negative out of the specified terminals
MIN NOM MAX UNIT
VDD Supply voltage 10 17 V
HB-HS Driver bootstrap voltage 10 17 V
HS Source terminal voltage(1) –8 600 V
HB Bootstrap pin voltage HS + 10 HS + 17 V
HI, LI, EN Input voltage with respect to VSS –4 17 V
VSS Logic ground –6(2) 5(3) V
TJ Junction temperature –40 125 °C
(1) Logic operational for HS of –8 V to 600 V at HB – HS = 12 V
(2) At VDD – COM = 10 V
(3) At VDD – COM = 15 V

6.4 Thermal Information

THERMAL METRIC(1) UCC27714 UNIT
D (SOIC)
PINS
RθJA Junction-to-ambient thermal resistance 72.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.8 °C/W
RθJB Junction-to-board thermal resistance 26.5 °C/W
ψJT Junction-to-top characterization parameter 3.6 °C/W
ψJB Junction-to-board characterization parameter 26.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At VDD = VHB = 15 V, VSS = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < 125°C, current are positive into and negative out of the specified terminal, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY BLOCK
VVDD(on) turn-on threshold voltage of VDD 8.4 9.1 9.8 V
VVDD(off) turn-off threshold voltage of VDD 7.9 8.6 9.3 V
VVDD(hys) Hysteresis of VDD 0.4 0.5 - V
VVHB(on) turn-on threshold voltage of VHB-VHS 7.7 8.3 9.0 V
VVHB(off) turn-off threshold voltage of VHB-VHS 6.7 7.25 8.05 V
VVHB(hys) Hysteresis of VHB-VHS 0.5 1.0 - V
IQDD Total quiescent VDD to VSS and COM supply current HI = LI = 0 V or 5 V, DC on/off state 750 1050 µA
IQCOM Quiescent VDD-COM supply current HI = LI = 0 V or 5 V, DC on/off state 175 350 µA
IQVSS Quiescent VDD-VSS supply current HI = LI = 0 V or 5 V, DC on/off state 550 750 µA
IQBS Quiescent HB-HS supply current HI = 0 V or 5 V, HO in DC on/off state 120 300 µA
IBL Bootstrap Supply Leakage Current HB = HS = 600 V 20 µA
INPUT AND ENABLE BLOCK
VINH, VENH Input pin (HI or LI) and enable pin (EN) High threshold 1.7 2.3 2.7 V
VINL, VENL Input pin (HI or LI) and enable pin (EN) low threshold 1.2 1.6 2.1 V
VINHYS, VENHYS Input pin (HI or LI) and enable pin (EN) threshold hysteresis 0.7 V
IINL HI, LI input low bias current HI, LI = 0 V -5 0 5 µA
IINH HI, LI input high bias current HI, LI = 5 V 3 65 µA
IENL EN input low bias current VEN = 0 V -90 -50 µA
IENH EN input high bias current VEN = 5 V -65 -25 µA
RHI Pull-down resistor on HI input pin 400 kΩ
RLI Pull-down resistor on LI input pin 400 kΩ
REN Pull-up resistor on enable pin 200 kΩ
OUTPUT BLOCK
VDD-VLOH LO output high voltage LI = 5 V, ILO = –20 mA 70 120 mV
VHB-VHOH HO output high voltage HI = 5 V, IHO = –20 mA 70 120 mV
VLOL LO output low voltage LI = 0 V, ILO = 20 mA 15 35 mV
VHOL HO output low voltage HI = 0 V, IHO = 20 mA 20 40 mV
RLOL, RHOL (2) LO, HO output pull down resistance ILO = 20 mA, IHO = 20 mA 1.45 Ω
RLOH, RHOH LO, HO output pull up resistance ILO = –20 mA, IHO= –20 mA 3.75 5.8 Ω
IGPK- (1) HO. LO output low short circuit pulsed current HI = L = 0 V, HO = LO = 15 V, PW < 10 µs 4 A
IGPK+ (1) HO. LO output high short circuit pulsed current H I= LI = 5 V, HO = LO = 0 V, PW < 10 µs 4 A
(1) Ensured by Design, Not tested in production
(2) ROH represents on-resistance of only the P-Channel MOSFET device in pull-up structure of UCC27714 output stage. Refer to Output Stage

6.6 Timing Requirements

MIN NOM MAX UNIT
DYNAMIC CHARACTERISTICS
tPDLH Turn-on propagation delay, LI to LO, HI to HO, HS = COM = 0 V or HS = 600 V 90 125 ns
tPDHL Turn-off propagation delay, LI to LO, HI to HO, HS = COM = 0 V or HS = 600 V 90 125 ns
tPDRM Low-to-high delay matching, HS = COM = 0 V 20 ns
tPDFM High-to-low delay matching, HS = COM = 0 V 20 ns
tRISE Turn-on rise time, 10% to 90%, HO/LO with 1000-pF load 15 30 ns
tFALL Turn-off fall time, 90% to 10%, HO/LO with 1000-pF load 15 30 ns
tON Minimum HI/LI ON pulse that changes output state, 0-V to 5-V input signal on HI and LI pins 40 100 ns
tOFF Minimum HI/LI OFF pulse that changes output state, 5-V to 0-V input signal on HI and LI pins 40 100 ns
UCC27714 timing_lusby6.gif Figure 1. Typical Test Timing Diagram

6.7 Typical Characteristics

UCC27714 Lowside_turnondelay.gif
Figure 2. Low-Side, Turn-On Propagation Delay vs Temperature
UCC27714 highside_turnondelay.gif
Figure 4. High-Side, Turn-On Propagation Delay vs Temperature
UCC27714 turnondelaymatching.gif
Figure 6. Turn-On Delay Matching vs Temperature
UCC27714 HI_HO_ONdelay_HS.gif
Figure 8. High-Side, Turn-On Propagation Delay vs Temperature
UCC27714 Lo_trise.gif
Figure 10. LO Rise Time with 1000-pF Load vs Temperature
UCC27714 HO_trise.gif
Figure 12. HO Rise Time with 1000-pF Load vs Temperature
UCC27714 VDD_UVLO_ON.png
Figure 14. VDD UVLO On Threshold vs Temperature
UCC27714 HB_UVLO_ON.png
Figure 16. VHB-VHS UVLO On Threshold vs Temperature
UCC27714 VDD_UVLO_HYS.png
Figure 18. VDD UVLO Hysteresis vs Temperature
UCC27714 IN_UVLO_ON.png
Figure 20. HI/LI/EN Pin High Threshold vs Temperature
UCC27714 IN_UVLO_HYS.png
Figure 22. HI/LI/EN Pin Hysteresis vs Temperature
UCC27714 Fig 24 V_LOH.png
Figure 24. LO Output High Voltage with 20-mA Load vs Temperature
UCC27714 V_HOH.gif
Figure 26. HO Output High Voltage with 20-mA Load vs Temperature
UCC27714 Fig 28 RDSON_HOL.png
Figure 28. HO Output Pull-Down Resistance vs Temperature
UCC27714 Fig 30 RDSON_HOH.png
Figure 30. HO Output Pull-Up Resistance vs Temperature
UCC27714 EN_OFF_RESPONSE_time.gif
Figure 32. EN OFF Response Time vs Temperature
UCC27714 IQCOM.png
Figure 34. Quiescent VDD to COM Supply Current vs Temperature
UCC27714 IBL.png
Figure 36. Bootstrap Supply Leakage Current vs Temperature
UCC27714 Fig 3 Lowside_tunroffdelay.png
Figure 3. Low-Side, Turn-Off Propagation Delay vs Temperature
UCC27714 highside_turnoffdelay.gif
Figure 5. High-Side, Turn-Off Propagation Delay vs Temperature
UCC27714 turnoffdelaymatching.gif
Figure 7. Turn-Off Delay Matching vs Temperature
UCC27714 HI_HO_OFFdelay_HS.gif
Figure 9. High-Side, Turn-Off Propagation Delay vs Temperature
UCC27714 Lo_tfall.gif
Figure 11. LO Fall Time with 1000-pF Load vs Temperature
UCC27714 HO_tfall.gif
Figure 13. HO Fall Time with 1000-pF Load vs Temperature
UCC27714 VDD_UVLO_OFF.png
Figure 15. VDD UVLO Off Threshold vs Temperature
UCC27714 HB_UVLO_OFF.png
Figure 17. VHB-VHS UVLO Off Threshold vs Temperature
UCC27714 HB_UVLO_HYS.png
Figure 19. VHB-VHS UVLO Hysteresis vs Temperature
UCC27714 IN_UVLO_OFF.png
Figure 21. HI/LI/EN Pin Low Threshold vs Temperature
UCC27714 V_LOL.gif
Figure 23. LO Output Low Voltage with 20-mA Load vs Temperature
UCC27714 V_HOL.gif
Figure 25. HO Output Low Voltage with 20-mA Load vs Temperature
UCC27714 RDSON_LOL.gif
Figure 27. LO Output Pull-Down Resistance vs Temperature
UCC27714 Fig 29 RDSON_LOH.png
Figure 29. LO Output Pull-Up Resistance vs Temperature
UCC27714 Fig 31 EN_ON_RESPONSE_time.png
Figure 31. EN ON Response Time vs Temperature
UCC27714 IQDD.png
Figure 33. Total Quiescent VDD to VSS and COM Supply Current vs Temperature
UCC27714 IQVSS.png
Figure 35. Quiescent VDD to VSS Supply Current vs Temperature
UCC27714 IQBS.png
Figure 37. Total Quiescent HB to HS Supply Current