JAJSJ67E may   2020  – july 2023 UCC28782

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Detailed Pin Description
      1. 8.3.1  BUR Pin (Programmable Burst Mode)
      2. 8.3.2  FB Pin (Feedback Pin)
      3. 8.3.3  REF Pin (Internal 5-V Bias)
      4. 8.3.4  VDD Pin (Device Bias Supply)
      5. 8.3.5  P13 and SWS Pins
      6. 8.3.6  S13 Pin
      7. 8.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 8.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 8.3.9  PWMH and AGND Pins
      10. 8.3.10 PWML and PGND Pins
      11. 8.3.11 SET Pin
      12. 8.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 8.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 8.3.14 BIN, BSW, and BGND Pins
      15. 8.3.15 XCD Pin
      16. 8.3.16 CS, VS, and FLT Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 8.4.2  Dead-Time Optimization
      3. 8.4.3  EMI Dither and Dither Fading Function
      4. 8.4.4  Control Law across Entire Load Range
      5. 8.4.5  Adaptive Amplitude Modulation (AAM)
      6. 8.4.6  Adaptive Burst Mode (ABM)
      7. 8.4.7  Low Power Mode (LPM)
      8. 8.4.8  First Standby Power Mode (SBP1)
      9. 8.4.9  Second Standby Power Mode (SBP2)
      10. 8.4.10 Startup Sequence
      11. 8.4.11 Survival Mode of VDD (INT_STOP)
      12. 8.4.12 Capacitor Voltage Balancing Function
      13. 8.4.13 Device Functional Modes for Bias Regulator Control
        1. 8.4.13.1 Mitigation of Switching Interaction with ACF Converter
        2. 8.4.13.2 Protection Functions for the Bias Regulator
        3. 8.4.13.3 BIN-Pin Related Protections
        4. 8.4.13.4 BSW-Pin Related Protections
      14. 8.4.14 System Fault Protections
        1. 8.4.14.1  Brown-In and Brown-Out
        2. 8.4.14.2  Output Over-Voltage Protection (OVP)
        3. 8.4.14.3  Input Over Voltage Protection (IOVP)
        4. 8.4.14.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 8.4.14.5  Over-Temperature Protection (OTP) on CS Pin
        6. 8.4.14.6  Programmable Over-Power Protection (OPP)
        7. 8.4.14.7  Peak Power Limit (PPL)
        8. 8.4.14.8  Output Short-Circuit Protection (SCP)
        9. 8.4.14.9  Over-Current Protection (OCP)
        10. 8.4.14.10 External Shutdown
        11. 8.4.14.11 Internal Thermal Shutdown
      15. 8.4.15 Pin Open/Short Protections
        1. 8.4.15.1 Protections on CS pin Fault
        2. 8.4.15.2 Protections on P13 pin Fault
        3. 8.4.15.3 Protections on RDM and RTZ pin Faults
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Circuit
      1. 9.2.1 Design Requirements for a 65-W USB-PD Adapter Application
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 9.2.2.2 Transformer Calculations
          1. 9.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 9.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 9.2.2.2.3 Primary Winding Turns (NP)
          4. 9.2.2.2.4 Secondary Winding Turns (NS)
          5. 9.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 9.2.2.2.6 Winding and Magnetic Core Materials
        3. 9.2.2.3 Clamp Capacitor Calculation
          1. 9.2.2.3.1 Primary-Resonance ACF
          2. 9.2.2.3.2 Secondary-Resonance ACF
        4. 9.2.2.4 Bleed-Resistor Calculation
        5. 9.2.2.5 Output Filter Calculation
        6. 9.2.2.6 Calculation of ZVS Sensing Network
        7. 9.2.2.7 Calculation of BUR Pin Resistances
        8. 9.2.2.8 Calculation of Compensation Network
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  General Considerations
      2. 11.1.2  RDM and RTZ Pins
      3. 11.1.3  SWS Pin
      4. 11.1.4  VS Pin
      5. 11.1.5  BUR Pin
      6. 11.1.6  FB Pin
      7. 11.1.7  CS Pin
      8. 11.1.8  BIN Pin
      9. 11.1.9  BSW Pin
      10. 11.1.10 AGND Pin
      11. 11.1.11 BGND Pin
      12. 11.1.12 PGND Pin
      13. 11.1.13 EP Thermal Pad
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

BUR Pin (Programmable Burst Mode)

The voltage at the BUR pin (VBUR) sets a target peak current-sense threshold at the CS pin (VCST(BUR)) which programs the onset of adaptive burst mode (ABM). VBUR also determines the clamped peak current level of switching cycles in each burst packet. When VBUR is set higher, ABM will start at heavier output load conditions with higher peak primary current, so the benefit is higher light-load efficiency but the side effect is larger burst-mode output voltage ripple. Therefore, 50% to 60% of output load at high line is the recommended highest load condition to enter ABM (IO(BUR)) for both Si and GaN-based ACF designs.

The relationship between VBUR and VCST(BUR) is a constant gain of KBUR-CST, so targeting VCST(BUR) just requires properly selecting the resistor divider on the BUR pin formed by RBUR1 and RBUR2. VBUR should be set between 0.7 V and 2.4 V, which constitute internal limits. If VBUR is less than 0.7 V, VCST(BUR) holds at 0.7 V / KBUR-CST. If VBUR is higher than 2.4 V, VCST(BUR) holds at 2.4 V / KBUR-CST. Targeting an excessively low or high percentage of load for entering ABM will engage one of these internal limits.

Equation 1. GUID-19693839-4273-4143-87BA-1015DDF6F421-low.gif

In order to enhance the mode transition between ABM and LPM, a programmable offset voltage (ΔVBUR(LPM)) is generated on top of the VBUR setting in ABM through an internal 2.7-μA current source (IBUR(LPM)), as shown in Figure 8-1. In ABM, VBUR is set through the resistor voltage divider to fulfill the target average efficiency. On transition from ABM to LPM, IBUR(LPM) is enabled in LPM and flows out of the BUR pin, so ΔVBUR(LPM) can be programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

Equation 2. GUID-5E27A1F0-13BE-4D0D-97D5-05184DADEE58-low.gif
GUID-7BB31E7E-DF54-40DE-B0BF-1BB9083B4334-low.gifFigure 8-1 Hysteresis Voltage Generation on BUR Pin

When VBUR steps higher on transition into LPM, the initial peak magnetizing current in LPM is increased with larger energy per switching cycle in each burst packet. This increases the output voltage which forces higher feedback current to restore regulation. Higher feedback current causes UCC28782 to stay in LPM, forming a hysteresis effect. If ΔVBUR(LPM) is designed too small, it is possible that mode toggling between LPM and ABM can occur resulting in audible noise. For that situation, ΔVBUR(LPM) greater than 100 mV is recommended.

To minimize the effects of external noise coupling on VBUR, a filter capacitor on the BUR pin (CBUR) may be needed. CBUR needs to be properly designed to minimize the delay in generating ΔVBUR during mode transitions. It is recommended that CBUR should be sized small enough to ensure ΔVBUR(LPM) settles within 40 μs, corresponding to the burst frequency of 25 kHz in LPM (fLPM). Based on three RC time constants, representing 95% of a settled steady-state value from a step response, the design guide for CBUR is expressed as

Equation 3. GUID-6E1F278D-9CDB-40D0-A9C6-E05782F0A25E-low.gif

In order to enhance the mode transition between ABM and AAM, a programmable offset voltage (ΔVBUR(AAM)) is generated to lower the VBUR with an internal 5-μA pull-down current (IBUR(AAM)), as shown in Figure 8-1. After transition from ABM to AAM, IBUR(AAM) is enabled in AAM and flows into the BUR pin, so ΔVBUR(AAM) is also programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

Equation 4. GUID-0551B200-C3E4-44B8-8710-337C26B2D514-low.gif

When VBUR reduces after transition to AAM, the initial peak magnetizing current in AAM is reduced with less energy per switching cycle, which forces UCC28782 to stay in AAM. If ΔVBUR(AAM) is too small, it is possible that either mode toggling between ABM and AAM or low-frequency ABM burst packets less than 20 kHz can occur and result in audible noise concern. For that situation, ΔVBUR(AAM) greater than 150 mV is recommended. In some power stage designs, LPM in hard switching condition may cover a wider output load current range, so the light-load efficiency in LPM may be lower than ABM with ZVS condition. Besides, the ABM-to-AAM mode transition may be affected potentially when the load current condition of LPM-to-ABM transition is too close to the load current condition of ABM-AAM transition.

In order to narrow down the output load current range in LPM, lower VBUR(ABM), smaller ΔVBUR(LPM), larger ROPP, and smaller CCS help to reduce the peak magnetizing current in LPM. If the LPM energy needs to be further reduced but VBUR in AAM is limited by the 0.7-V minimum programmable level, the optional application circuit in Figure 8-2 can be considered. When the output load current is reduced, duty cycle of each burst packet becomes smaller, so as the duty cycle of RUN-pin voltage. CBUR is discharged by the RUN driver through the small-signal diode (DBUR) and the current limit resistor (RRUN). Proper selection of RRUN value can further reduce VBUR(ABM) when the load current is reduced close to the transition point from ABM to LPM. One example BUR-pin setting is RBUR1 = 182 kΩ, RBUR2 = 37.4 kΩ, CBUR = 330 pF, and RRUN = 20 kΩ.

GUID-04160FFA-D44E-4349-83AF-EFAF8E99E458-low.gifFigure 8-2 Optional Application Circuit to Reduce VBUR in LPM