SCBS809G December   2005  – September 2017 UCC2895-EP

PRODUCTION DATA.  

  1. 1Features
  2. 2Description
  3. 3Revision History
  4. 4Pin Configuration and Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  6. 6Application and Implementation
    1. 6.1 Programming DELAB, DELCD, and Adaptive Delay Set (ADS)
    2. 6.2 Circuit Description
  7. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

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発注情報

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Programming DELAB, DELCD, and Adaptive Delay Set (ADS)

The UCC2895-EP allows the user to set the delay between switch commands within each leg of the full-bridge power circuit, according to the formula from the data sheet:

UCC2895-EP equation5_cbs809.gif

For this equation, VDEL is determined in conjunction with the desire to utilize (or not utilize) the ADS feature from:

UCC2895-EP equation3_cbs809.gif

Figure 9 shows the resistors needed to program the delay periods and the ADS function.

UCC2895-EP resistors_cbs809.gif Figure 9. Resistors Needed In Programming

The ADS allows the user to vary the delay times between switch commands within each of the converter’s two legs. The delay-time modulation is implemented by connecting ADS (pin 11) to CS, GND, or a resistive divider from CS to GND to set VADS. From the previous equation for VDEL, if ADS is tied to GND, VDEL rises in direct proportion to VCS, causing a decrease in tDELAY as the load increases. In this condition, the maximum value of VDEL is 2 V. If ADS is connected to a resistive divider between CS and GND, the term (VCS – VDS) becomes smaller, reducing the level of VDEL. This decreases the amount of delay modulation. In the limit of ADS tied to CS, VDEL = 0.5 V and no delay modulation occurs. In the case with maximum delay modulation (ADS = GND) when the circuit goes from light load to heavy load, the variation of VDEL is from 0.5 V to 2 V. This causes the delay times to vary by a 4:1 ratio as the load is changed.

The ability to program an adaptive delay is a desirable feature because the optimum delay time is a function of the current flowing in the primary winding of the transformer, and can change by a factor of 10:1 or more as circuit loading changes. Reference [1] delves into the many interrelated factors for choosing the optimum delay times for the most efficient power conversion and illustrates an external circuit to enable ADS using the UC2879. Implementing this adaptive feature is simplified in the UCC2895-EP controller, giving the user the ability to tailor the delay times to suit a particular application, with a minimum of external parts.

[1] L. Balogh, "Design Review: 100W, 400 kHz, DC/DC Converter With Current Doubler Synchronous Rectification Achieves 92% Efficiency," Unitrode Power Supply Design Seminar Manual, Unitrode Corporation, 1996, Topic 2.

UCC2895-EP resis_prog_cbs809.gif Figure 10. Resistors Needed For Programming
UCC2895-EP timing_diag_cbs809.gif Figure 11. UCC2895-EP Timing (No Output Delay Shown)
UCC2895-EP app_inf_cont_cbs809.gif Figure 12. Block Diagram

Circuit Description

UCC2895-EP osc_bd_cbs809.gif Figure 13. Oscillator Block Diagram
UCC2895-EP del_set_bd_cbs809.gif Figure 14. ADS Block Diagram
UCC2895-EP del_bd2_cbs809.gif Figure 15. Delay Block Diagram (One Delay Block Per Output)