JAJSAO3G
January 2007 – April 2025
LM5574
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
High Voltage Start-Up Regulator
6.3.2
Oscillator and Sync Capability
6.3.3
Error Amplifier and PWM Comparator
6.3.4
Ramp Generator
6.3.5
Maximum Duty Cycle, Input Dropout Voltage
6.3.6
Current Limit
6.3.7
Soft Start
6.3.8
Boost Pin
6.3.9
Thermal Protection
6.4
Device Functional Modes
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Custom Design With WEBENCH® Tools
7.2.2.2
External Components
7.2.2.3
R3 (R)T
7.2.2.4
L1-Inductor
7.2.2.5
C3 (C)RAMP
7.2.2.6
C9-Output Capacitor
7.2.2.7
D1-Async Diode
7.2.2.8
C1-Input Capacitor
7.2.2.9
C8-VCC Capacitor
7.2.2.10
C7-BST Capacitor
7.2.2.11
C4- SS Capacitor
7.2.2.12
R5, R6- Feedback Resistors
7.2.2.13
R1, R2, C2-SD Pin Components
7.2.2.14
R4, C5, C6-Compensation Components
7.2.2.15
Bias Power Dissipation Reduction
7.2.3
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Example
7.4.3
Power Dissipation
7.4.4
Thermal Considerations
8
Device and Documentation Support
8.1
Device Support
8.1.1
サード・パーティ製品に関する免責事項
8.1.2
Development Support
8.1.2.1
Custom Design With WEBENCH® Tools
8.2
Documentation Support
8.2.1
Related Documentation
8.3
ドキュメントの更新通知を受け取る方法
8.4
サポート・リソース
8.5
Trademarks
8.6
静電気放電に関する注意事項
8.7
用語集
9
Revision History
10
Mechanical, Packaging, and Orderable Information
6.2
Functional Block Diagram