JAJSCL6A November   2016  – January 2022 UCC20520

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 PWM Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC20520
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
        3. 8.4.2.3 39
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing PWM Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Dead Time Setting Guidelines
        8. 9.2.2.8 Application Circuits with Output Stage Negative Bias
        9. 9.2.2.9 56
      3. 9.2.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
      1. 11.3.1 Certifications
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

5 Pin Configuration and Functions

GUID-83A186AF-684D-41F7-89EB-96945026CC41-low.gif Figure 5-1 DW Package, 16-Pin SOIC (Top View)
Table 5-1 Pin Functions
PIN TYPE1 DESCRIPTION
NAME NO.
DISABLE 5 I Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity.
DT 6 I Programmable dead time function.

Tying DT to VCCI disables the DT function with dead time ≅ 0 ns. Leaving DT open sets the dead time to <15 ns. Placing a 500-Ω to 500-kΩ resistor (RDT) between DT and GND adjusts dead time according to: DT (in ns) = 10 × RDT (in kΩ). It is recommended to parallel a ceramic capacitor, ≥2.2-nF, with RDT to achieve better noise immunity.
GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground.
NC 2 – No connection.
NC 7 – No connection.
NC 12 – No connection.
NC 13 – No connection.
OUTA 15 O Output of driver A. Connect to the gate of the A channel FET or IGBT. Output A is in phase with PWM input with a propagation delay
OUTB 10 O Output of driver B. Connect to the gate of the B channel FET or IGBT. Output B is always complementary to output A with a programmed dead time.
PWM 1 I PWM input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open.
VCCI 3 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible.
VCCI 8 P Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA 16 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible.
VDDB 11 P Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located as close to the device as possible.
VSSA 14 P Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB 9 P Ground for secondary-side driver B. Ground reference for secondary side B channel.
  1. I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power