JAJSE26 October   2017 MSP432E411Y


  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 212-Pin ZAD (NFBGA) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. Power and Brownout
          1. VDDA Levels
          2. VDD Levels
          3. VDDC Levels
          4. VDD Glitch Response
          5. VDD Droop Response
      3. 5.15.3  Reset Timing
      4. 5.15.4  Clock Specifications
        1. PLL Specifications
          1. PLL Configuration
        2. PIOSC Specifications
        3. Low-Frequency Oscillator Specifications
        4. Hibernation Low-Frequency Oscillator Specifications
        5. Main Oscillator Specifications
        6. Main Oscillator Specification WIth ADC
        7. System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
      6. 5.15.6  Hibernation Module
      7. 5.15.7  Flash Memory
      8. 5.15.8  EEPROM
      9. 5.15.9  Input/Output Pin Characteristics
        1. Types of I/O Pins and ESD Protection
          1. Hibernate WAKE pin
          2. Nonpower I/O Pins
      10. 5.15.10 External Peripheral Interface (EPI)
      11. 5.15.11 Analog-to-Digital Converter (ADC)
      12. 5.15.12 Synchronous Serial Interface (SSI)
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
      14. 5.15.14 Ethernet Controller
        1. DC Characteristics
        2. Clock Characteristics for Ethernet
        3. AC Characteristics
      15. 5.15.15 Universal Serial Bus (USB) Controller
      16. 5.15.16 LCD Controller
        1. LCD Interface Display Driver (LIDD Mode)
          1. Hitachi Mode
          2. Motorola 6800 Mode
          3. Intel 8080 Mode
        2. LCD Raster Mode
      17. 5.15.17 Analog Comparator
      18. 5.15.18 Pulse-Width Modulator (PWM)
      19. 5.15.19 Emulation and Debug
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. Ethernet MAC and PHY
        2. Controller Area Network (CAN)
        3. Universal Serial Bus (USB)
        4. Universal Asynchronous Receiver/Transmitter (UART)
        5. 1-Wire Master Module
        6. Inter-Integrated Circuit (I2C)
        7. Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. Direct Memory Access (DMA)
        2. System Control and Clocks
        3. Programmable Timers
        4. Capture Compare PWM (CCP) Pins
        5. Hibernation (HIB) Module
        6. Watchdog Timers
        7. Programmable GPIOs
      8. 6.5.8  LCD Controller
      9. 6.5.9  Advanced Motion Control
        1. Pulse Width Modulation (PWM)
        2. Quadrature Encoder With Index (QEI) Module
      10. 6.5.10 Analog
        1. ADC
        2. Analog Comparators
      11. 6.5.11 JTAG and Arm Serial Wire Debug
      12. 6.5.12 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 使い始めと次の手順
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 Community Resources
    6. 8.6 商標
    7. 8.7 静電気放電に関する注意事項
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

Detailed Description


The SimpleLink MSP432E411Y Arm Cortex-M4 microcontroller (MCU) provides top performance and advanced integration. The MSP432E4 product family is positioned for cost-effective applications requiring significant control processing and connectivity capabilities such as the following:

  • Industrial communication equipment
  • Network appliances, gateways, and adapters
  • Residential and commercial site monitoring and control
  • Remote connectivity and monitoring
  • Security and access systems
  • HMI control panels
  • Factory automation control
  • Test and measurement equipment
  • Fire and security systems
  • Motion control and power inversion
  • Medical instrumentation
  • Gaming equipment
  • Electronic point-of-sale (POS) displays
  • Smart energy and smart grid solutions
  • Intelligent lighting control
  • Vehicle tracking

The MSP432E411Y MCU integrates a large variety of rich communication features to enable a new class of highly connected designs that can support critical, real-time control with a balance between performance and power. The MCU features integrated communication peripherals and other high-performance analog and digital functions to offer a strong foundation for many different target uses, from human-machine interface to networked system management controllers.

In addition, the MSP432E411Y MCU offers the advantages of widely available development tools from Arm, System-on-Chip (SoC) infrastructure, and a large user community. Additionally, this MCU uses the Thumb-compatible Thumb-2 instruction set from Arm to reduce memory requirements and, thereby, cost. Finally, when using the SimpleLink SDK, the MSP432E411Y MCU is code-compatible with all members of the SimpleLink series, providing flexibility to fit precise needs.

TI offers a complete solution to get to market quickly, with evaluation and development boards; white papers and application notes; an easy-to-use peripheral driver library; and a strong support, sales, and distributor network.

Functional Block Diagram

Figure 6-1 shows the features on the MSP432E411Y MCU. Two on-chip buses connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back access performance than the APB bus.

MSP432E411Y msp432e411y-high-level-block-diagram.gif Figure 6-1 MSP432E411Y High-Level Block Diagram

Arm Cortex-M4F Processor Core

All members of the MSP432E4 family are designed around an Arm Cortex-M processor core. The Arm Cortex-M processor provides the core for a high-performance low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.

Processor Core

Features of the processor core include:

  • 32-bit Arm Cortex-M4F architecture optimized for small-footprint embedded applications
  • 120-MHz operation; 150 DMIPS performance
  • Outstanding processing performance combined with fast interrupt handling
  • Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for MCU-class applications.
    • Single-cycle multiply instruction and hardware divide
    • Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral control
    • Unaligned data access, enabling data to be efficiently packed into memory
  • IEEE 754-compliant single-precision floating-point unit (FPU)
  • 16-bit SIMD vector processing unit
  • Fast code execution permits slower processor clock or increases sleep mode time
  • Harvard architecture characterized by separate buses for instruction and data
  • Efficient processor core, system, and memories
  • Hardware division and fast digital-signal-processing orientated multiply accumulate
  • Saturating arithmetic for signal processing
  • Deterministic high-performance interrupt handling for time-critical applications
  • Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality
  • Enhanced system debug with extensive breakpoint and trace capabilities
  • Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing
  • Migration from the Arm7® processor family for better performance and power efficiency
  • Optimized for single-cycle flash memory use up to specific frequencies; see the Internal Memory chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for more information.
  • Ultra-low-power consumption with integrated sleep modes

System Timer (SysTick)

SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example:

  • An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine
  • A high-speed alarm timer using the system clock
  • A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter
  • A simple counter used to measure time to completion and time used
  • An internal clock-source control based on missing or meeting durations

Nested Vectored Interrupt Controller (NVIC)

The NVIC and Cortex-M4F core prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The interrupt vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and restoration. Software can set 8 priority levels on 7 exceptions (system handlers) and 109 interrupts.

  • Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining (these values reflect no FPU stacking)
  • External nonmaskable interrupt signal (NMI) available for immediate execution of NMI handler for safety critical applications
  • Dynamically reprioritizable interrupts
  • Exceptional interrupt handling through hardware implementation of required register manipulations

Table 6-1 lists the interrupts.

Table 6-1 Interrupts

0 to 15 0x0000.0000 to 0x0000.003C Processor exceptions
16 0 0x0000.0040 GPIO Port A
17 1 0x0000.0044 GPIO Port B
18 2 0x0000.0048 GPIO Port C
19 3 0x0000.004C GPIO Port D
20 4 0x0000.0050 GPIO Port E
21 5 0x0000.0054 UART0
22 6 0x0000.0058 UART1
23 7 0x0000.005C SSI0
24 8 0x0000.0060 I2C0
25 9 0x0000.0064 PWM fault
26 10 0x0000.0068 PWM generator 0
27 11 0x0000.006C PWM generator 1
28 12 0x0000.0070 PWM generator 2
29 13 0x0000.0074 QEI0
30 14 0x0000.0078 ADC0 sequence 0
31 15 0x0000.007C ADC0 sequence 1
32 16 0x0000.0080 ADC0 sequence 2
33 17 0x0000.0084 ADC0 sequence 3
34 18 0x0000.0088 Watchdog timers 0 and 1
35 19 0x0000.008C 16-/32-Bit Timer 0A
36 20 0x0000.0090 16-/32-Bit Timer 0B
37 21 0x0000.0094 16-/32-Bit Timer 1A
38 22 0x0000.0098 16-/32-Bit Timer 1B
39 23 0x0000.009C 16-/32-Bit Timer 2A
40 24 0x0000.00A0 16-/32-Bit Timer 2B
41 25 0x0000.00A4 Analog comparator 0
42 26 0x0000.00A8 Analog comparator 1
43 27 0x0000.00AC Analog comparator 2
44 28 0x0000.00B0 System control
45 29 0x0000.00B4 Flash memory control
46 30 0x0000.00B8 GPIO port F
47 31 0x0000.00BC GPIO port G
48 32 0x0000.00C0 GPIO port H
49 33 0x0000.00C4 UART2
50 34 0x0000.00C8 SSI1
51 35 0x0000.00CC 16-/32-Bit Timer 3A
52 36 0x0000.00D0 16-/32-Bit Timer 3B
53 37 0x0000.00D4 I2C1
54 38 0x0000.00D8 CAN0
55 39 0x0000.00DC CAN1
56 40 0x0000.00E0 Ethernet MAC
57 41 0x0000.00E4 HIB
58 42 0x0000.00E8 USB MAC
59 43 0x0000.00EC PWM generator 3
60 44 0x0000.00F0 µDMA 0 Software
61 45 0x0000.00F4 µDMA 0 Error
62 46 0x0000.00F8 ADC1 sequence 0
63 47 0x0000.00FC ADC1 sequence 1
64 48 0x0000.0100 ADC1 sequence 2
65 49 0x0000.0104 ADC1 sequence 3
66 50 0x0000.0108 EPI0
67 51 0x0000.010C GPIO port J
68 52 0x0000.0110 GPIO port K
69 53 0x0000.0114 GPIO port L
70 54 0x0000.0118 SSI2
71 55 0x0000.011C SSI3
72 56 0x0000.0120 UART3
73 57 0x0000.0124 UART4
74 58 0x0000.0128 UART5
75 59 0x0000.012C UART6
76 60 0x0000.0130 UART7
77 61 0x0000.0134 I2C2
78 62 0x0000.0138 I2C3
79 63 0x0000.013C Timer 4A
80 64 0x0000.0140 Timer 4B
81 65 0x0000.0144 Timer 5A
82 66 0x0000.0148 Timer 5B
83 67 0x0000.014C Floating-Point Exception (imprecise)
84 68 Reserved
85 69 Reserved
86 70 0x0000.0158 I2C4
87 71 0x0000.015C I2C5
88 72 0x0000.0160 GPIO port M
89 73 0x0000.0164 GPIO port N
90 74 Reserved
91 75 0x0000.016C Tamper
92 76 0x0000.017 GPIO port P (Summary or P0)
93 77 0x0000.0174 GPIO port P1
94 78 0x0000.0178 GPIO port P2
95 79 0x0000.017C GPIO port P3
96 80 0x0000.0180 GPIO port P4
97 81 0x0000.0184 GPIO port P5
98 82 0x0000.0188 GPIO port P6
99 83 0x0000.018C GPIO port P7
100 84 0x0000.0190 GPIO port Q (summary or Q0)
101 85 0x0000.0194 GPIO port Q1
102 86 0x0000.0198 GPIO port Q2
103 87 0x0000.019C GPIO port Q3
104 88 0x0000.01A0 GPIO port Q4
105 89 0x0000.01A4 GPIO port Q5
106 90 0x0000.01A8 GPIO port Q6
107 91 0x0000.01AC GPIO port Q7
108 92 0x0000.01B0 GPIO port R
109 93 0x0000.01B4 GPIO port S
110 94 0x0000.01B8 SHA/MD5
111 95 0x0000.01BC AES
112 96 0x0000.01C0 DES
113 97 0x0000.01C4 LCD
114 98 0x0000.01C8 16-/32-Bit Timer 6A
115 99 0x0000.01CC 16-/32-Bit Timer 6B
116 100 0x0000.01D0 16-/32-Bit Timer 7A
117 101 0x0000.01D4 16-/32-Bit Timer 7B
118 102 0x0000.01D8 I2C6
119 103 0x0000.01DC I2C7
120 104 Reserved
121 105 0x0000.01E4 1-Wire
122 106 Reserved
123 107 Reserved
124 108 Reserved
125 109 0x0000.01F4 I2C8
126 110 0x0000.01F8 I2C9
127 111 0x0000.01FC GPIO port T

System Control Block (SCB)

The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions.

Memory Protection Unit (MPU)

The MPU supports the standard Arm7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system.

Floating-Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply-and-accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.

  • 32-bit instructions for single-precision (C float) data-processing operations
  • Combined multiply and accumulate instructions for increased precision (fused MAC)
  • Hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square-root
  • Hardware support for denormals and all IEEE rounding modes
  • 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
  • Decoupled 3-stage pipeline

On-Chip Memory

The following on-chip memories are supported:

  • 256KB of single-cycle SRAM
  • 1024KB of flash memory
  • 6KB of EEPROM
  • Internal ROM loaded with SimpleLink SDK software:
    • Peripheral driver library
    • Bootloader


The MSP432E411Y MCU provides 256KB of single-cycle on-chip SRAM. The internal SRAM of the device is at offset 0x2000.0000 of the device memory map.

The SRAM is implemented using four 32-bit-wide interleaving SRAM banks (separate SRAM arrays), which allow for increased speed between memory accesses. The SRAM memory provides nearly 2 GBps of memory bandwidth at a 120-MHz clock frequency.

Because read-modify-write (RMW) operations are time consuming, Arm has introduced bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in an atomic operation.

Data can be transferred to and from SRAM by the following masters:

  • µDMA
  • USB
  • LCD controller
  • Ethernet controller

Flash Memory

The MSP432E411Y MCU provides 1024KB of on-chip flash memory. The flash memory is configured as four banks of 16K × 128 bits (4 × 256KB total) that are 2-way interleaved. Memory blocks can be marked as read only or execute only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or a debugger.

Two sets of instruction prefetch buffers provide enhanced performance and power savings. Each prefetch buffer is 2 × 256 bits and can be combined as a 4 × 256-bit prefetch buffer.

The flash can also be accessed by the µDMA in run mode.


The ROM is preprogrammed with the following software and programs:

  • Peripheral driver library
  • Bootloader

The SimpleLink MSP432E4 SDK driver library is a royalty-free software library for controlling on-chip peripherals with a bootloader capability. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library is designed to take full advantage of the stellar interrupt performance of the Arm Cortex-M4F core. No special pragmas or custom assembly code prologue or epilogue functions are required. For applications that require in-field programmability, the royalty-free bootloader can act as an application loader and support in-field firmware updates.


The EEPROM includes the following features:

  • 6KB of memory accessible as 1536 32-bit words
  • 96 blocks of 16 words (64 bytes) each
  • Built-in wear leveling
  • Access protection per block
  • Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock codes (application selectable)
  • Interrupt support for write completion to avoid polling
  • Endurance of 500k writes (when writing at fixed offset in every alternate page in circular fashion) to 15M operations (when cycling through two pages) per each 2-page block.

Memory Map

The device supports a 4GB address space that is divided into eight 512MB zones (see Figure 6-2).

MSP432E411Y device_memory_zones.gif Figure 6-2 Device Memory Zones


External Peripheral Interface (EPI)

The EPI provides access to external devices using a parallel path. Unlike communications peripherals such as SSI, UART, and I2C, the EPI acts as a bus to external peripherals and memory.

The EPI has the following features:

  • 8-, 16-, or 32-bit dedicated parallel bus for external peripherals and memory
  • Memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from SDRAM, SRAM, and flash memory
  • Blocking and nonblocking reads
  • Separates processor from timing details through use of an internal write FIFO
  • Efficient transfers using µDMA
    • Separate channels for read and write
    • Read channel request asserted by programmable levels on the internal Nonblocking Read FIFO (NBRFIFO)
    • Write channel request asserted by empty on the internal Write FIFO (WFIFO)

The EPI supports three primary functional modes: SDRAM mode, traditional host-bus mode, and general-purpose mode. The EPI module also provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same way as a communication mechanism and is speed-controlled using clocking.

  • SDRAM mode
    • Supports ×16 (single data rate) SDRAM at up to 60 MHz
    • Supports low-cost SDRAMs up to 64MB (512 Mb)
    • Includes automatic refresh and access to all banks and rows
    • Includes a sleep (standby) mode to keep contents active with minimal power draw
    • Multiplexed address and data interface for reduced pin count
  • Host-bus mode
    • Traditional ×8 and ×16 MCU bus interface capabilities
    • Similar device compatibility options as PIC, ATmega, 8051, and others
    • Access to SRAM, NOR flash memory, and other devices, with up to 1MB of addressing in nonmultiplexed mode and 256MB in multiplexed mode (512MB in host bus 16 mode with no byte selects)
    • Support for up to 512Mb PSRAM in quad chip select mode, with dedicated configuration register read and write enable
    • Support of both muxed and demuxed address and data
    • Access to a range of devices supporting the nonaddress FIFO ×8 and ×16 interface variant, with support for external FIFO (XFIFO) EMPTY and FULL signals
    • Speed controlled, with read and write data wait-state counters
    • Support for read or write burst mode to Host Bus
    • Multiple chip-select modes including single, dual, and quad chip selects, with and without ALE
    • External iRDY signal provided for stall capability of reads and writes
    • Manual chip-enable (or use extra address pins)
  • General-purpose mode
    • Wide parallel interfaces for fast communications with CPLDs and FPGAs
    • Data widths up to 32 bits
    • Data rates up to 150 MB/second
    • Optional "address" sizes from 4 bits to 20 bits
    • Optional clock output, read and write strobes, framing (with counter-based size), and clock-enable input
  • General parallel GPIO
    • 1 to 32 bits, FIFO with speed control
    • Useful for custom peripherals or for digital data acquisition and actuator controls

Cyclical Redundancy Check (CRC)

The CRC computation module is for uses such as message transfer and safety system checks. This module can be used with the AES and DES modules. The CRC has the following features:

  • Support four major CRC forms:
    • CRC16-CCITT as used by CCITT/ITU X.25
    • CRC16-IBM as used by USB and ANSI
    • CRC32-IEEE as used by IEEE 802.3 and MPEG-2
    • CRC32C as used by G.Hn
  • Allows word and byte feed
  • Supports automatic initialization and manual initialization
  • Supports MSb and LSb
  • Supports CCITT post-processing
  • Can be fed by µDMA, flash memory, and code

Advanced Encryption Standard (AES) Accelerator

The AES accelerator module provides hardware-accelerated data encryption and decryption operations based on a binary key. The AES module is a symmetric cipher module that supports a 128-, 192-, or 256-bit key in hardware for both encryption and decryption.

The AES has following features:

  • Support for basic AES encryption and decryption operations:
    • Galois/counter mode (GCM) with basic GHASH operation
    • Counter mode with CBC-MAC (CCM)
    • XTS mode
  • Availability of the following feedback operating modes:
    • Electronic code book mode (ECB)
    • Cipher block chaining mode (CBC)
    • Counter mode (CTR)
    • Cipher feedback mode (CFB), 128-bit
    • F8 mode
  • Key sizes 128-, 192-, and 256-bits
  • Support for CBC_MAC and Fedora 9 (F9) authentication modes
  • Basic GHASH operation (when selecting no encryption)
  • Key scheduling in hardware
  • Support for µDMA transfers
  • Fully synchronous design

Data Encryption Standard (DES) Accelerator

The DES module provides hardware accelerated data encryption and decryption functions. The module runs either the single DES or the triple DES (3DES) algorithm and supports electronic codebook (ECB), cipher block chaining (CBC), and cipher feedback (CFB) modes of operation.

The DES accelerator includes the following main features:

  • DES/3DES encryption and decryption algorithm compliant with the FIPS 180-3 standard
  • Feedback modes: ECB, CBC, CFB
  • Host interrupt or µDMA driven modes of operation. µDMA support for data and context in and result out
  • Fully synchronous design
  • Internal wide-bus interface

Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator

The SHA/MD5 module provides hardware-accelerated hash functions and can run:

  • MD5 message digest algorithm developed by Ron Rivest in 1991
  • SHA-1 algorithm compliant with the FIPS 180-3 standard
  • SHA-2 (SHA-224 and SHA-256) algorithm compliant with the FIPS 180-3 standard
  • Hash message authentication code (HMAC) operation

The algorithms produce a condensed representation of a message or a data file, which can then be used to verify the message integrity.

The SHA/MD5 accelerator module includes the following main features:

  • Hashing of 0 to (233 – 2) bytes of data [of which (232 – 1) bytes are in one pass] using the MD5, SHA-1, SHA-224, or SHA-256 hash algorithm (byte granularity only, no support for bit granularity)
  • Automatic HMAC key preprocessing for HMAC keys up to 64 bytes
  • Host-assisted HMAC key preprocessing for HMAC keys larger than 64 bytes
  • HMAC from precomputes (inner and outer digest) for improved performance on small blocks
  • Supports µDMA operation for data and context in and result out transfers
  • Supports interrupt to read the digest (signature)

Serial Communications Peripherals

Both asynchronous and synchronous serial communications are supported with:

  • 10/100 Ethernet MAC with advanced IEEE 1588 PTP hardware and both media independent interface (MII) and reduced MII (RMII) support; integrated PHY provided
  • Two CAN 2.0 A and B controllers
  • USB 2.0 controller OTG, host, or device with optional high speed using external PHY through ULPI interface
  • Eight UARTs with IrDA, 9-bit, and ISO 7816 support
  • 1-wire master module that can provide power and data over one bidirectional wire
  • Ten I2C modules with four transmission speeds including high-speed mode
  • Four Quad Synchronous Serial Interface (QSSI) modules with bi- and quad-SSI support

The following sections provide more detail on each of these communications functions.

Ethernet MAC and PHY

The Ethernet controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface with the following features:

  • Conforms to the IEEE 802.3 specification
    • 10BASE-T and 100BASE-TX IEEE-802.3 compliant
    • Supports 10- and 100-Mbps data transmission rates
    • Supports full-duplex and half-duplex (CSMA/CD) operation
    • Supports flow control and back pressure
    • Full-featured and enhanced auto-negotiation
    • Supports IEEE 802.1Q VLAN tag detection
  • Conforms to IEEE 1588-2002 timestamp PTP protocol and the IEEE 1588-2008 advanced timestamp specification
    • Transmit and receive frame timestamping
    • Precision time protocol
    • Flexible pulse per second output
    • Supports coarse and fine correction methods
  • Multiple addressing modes
    • Four MAC address filters
    • Programmable 64-bit hash filter for multicast address filtering
    • Promiscuous mode support
  • Processor offloading
    • Programmable insertion (TX) or deletion (RX) of preamble and start-of-frame data
    • Programmable generation (TX) or deletion (RX) of CRC and pad data
    • IP header and hardware checksum checking (IPv4, IPv6, TCP, UDP, ICMP)
  • Highly configurable
    • LED activity selection
    • Supports network statistics with RMON and MIB counters
    • Supports magic packet and wake-up frames
  • Efficient transfers using integrated µDMA
    • Dual-buffer (ring) or linked-list (chained) descriptors
    • Round-robin or fixed priority arbitration between TX and RX
    • Descriptors support transfer blocks size up to 8KB
    • Programmable interrupts for flexible system implementation
  • Physical media manipulation
    • MDI/MDI-X cross-over support
    • Register-programmable transmit amplitude
    • Automatic polarity correction and 10BASE-T signal reception
  • MII and RMII support

Controller Area Network (CAN)

CAN is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can use a differential balanced line like RS-485 or twisted-pair wire. Originally created for automotive purposes, it is now used in many embedded control applications (for example, industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 kbps at 500 m).

A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information.

Each of the two CAN units includes the following features:

  • CAN protocol version 2.0 part A/B
  • Bit rates up to 1 Mbps
  • 32 message objects with individual identifier masks
  • Maskable interrupt
  • Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
  • Programmable loopback mode for self-test operation
  • Programmable FIFO mode enables storage of multiple message objects
  • Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals

Universal Serial Bus (USB)

USB is a serial bus standard designed to allow connection and disconnection of peripherals using a standardized interface without rebooting the system.

One USB controller supports high-speed and full-speed multiple-point communications and complies with the USB 2.0 standard for high-speed function. The USB controller can have three configurations: USB device, USB host, and USB OTG (negotiated on-the-go as host or device when connected to other USB-enabled systems). Support for full-speed communication is provided by using the integrated USB PHY or optionally, a high-speed ULPI can communicate to an external PHY.

The USB module has the following features:

  • Complies with USB-IF (Implementer's Forum) certification standards
  • USB 2.0 high-speed (480 Mbps) operation with the integrated ULPI communicating with an external PHY
  • Link power-management support that uses link-state awareness to reduce power usage
  • Four transfer types: control, interrupt, bulk, and isochronous
  • 16 endpoints
    • 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint
    • 7 configurable IN endpoints and 7 configurable OUT endpoints
  • 4KB of dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size
  • VBUS droop detection and interrupt
  • Integrated USB DMA with bus master capability
    • Up to eight RX endpoint channels and up to eight TX endpoint channels are available.
    • Each channel can be separately programmed to operate in different modes.
    • Incremental burst transfers of 4, 8, 16, or unspecified length supported

Universal Asynchronous Receiver/Transmitter (UART)

A UART is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately.

Eight fully programmable 16C550-type UARTs are integrated. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the RX, TX, modem flow control, modem status, and error conditions. The module generates one combined interrupt when any of the interrupts are asserted and are unmasked.

The UARTs have the following features:

  • Programmable baud-rate generator allowing speeds up to 7.5 Mbps for regular speed (divide by 16) and 15 Mbps for high speed (divide by 8)
  • Separate 16×8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
  • Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered interface
  • FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
  • Standard asynchronous communication bits for start, stop, and parity
  • Line-break generation and detection
  • Fully programmable serial interface characteristics
    • 5, 6, 7, or 8 data bits
    • Even, odd, stick, or no-parity bit generation/detection
    • 1 or 2 stop bit generation
  • IrDA serial-IR (SIR) encoder and decoder providing
    • Programmable use of IrDA Serial Infrared (SIR) or UART I/O
    • Support of IrDA SIR encoder and decoder functions for data rates up to 115.2 kbps half-duplex
    • Support of normal 3/16 and low-power (1.41 to 2.23 µs) bit durations
    • Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration
  • Support for communication with ISO 7816 smart cards
  • Modem functionality available on the following UARTs:
    • UART0 (modem flow control and modem status)
    • UART1 (modem flow control and modem status)
    • UART2 (modem flow control)
    • UART3 (modem flow control)
    • UART4 (modem flow control)
  • EIA-485 9-bit support
  • Standard FIFO-level and end-of-transmission interrupts
  • Efficient transfers using µDMA
    • Separate channels for transmit and receive
    • Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level
    • Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level
  • The Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate the baud clock

1-Wire Master Module

1-Wire is a bidirectional serial communication protocol that provides both power and data over one wire. The 1-Wire Master module can interface with a multiple variety of slaves such as thermometers, mixed-signal devices, memory, and authentication devices.

The 1-Wire Master module supports the following features:

  • Supports standard and overdrive speeds, including a late-sample mechanism
  • Allows transfers of send, receive, and bidirectional bits
  • Data size transfers of 1, 2, 3, or 4 bytes with subbyte search and enumeration support
  • Interrupt capability for transaction pacing and line error
  • Optional 2-wire support for isolated lines and high-voltage use
  • Efficient transfers using µDMA

Inter-Integrated Circuit (I2C)

The I2C bus provides bidirectional data transfer through a 2-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus can also be used for system testing and diagnostic purposes in product development and manufacture.

Each device on the I2C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts.

The I2C modules include the following features:

  • Devices on the I2C bus can be designated as either a master or a slave
    • Supports both transmitting and receiving data as either a master or a slave
    • Supports simultaneous master and slave operation
  • Four I2C modes
    • Master transmit
    • Master receive
    • Slave transmit
    • Slave receive
  • Two 8-entry FIFOs for receive and transmit data
    • FIFOs can be independently assigned to master or slave
  • Four transmission speeds:
    • Standard (100 kbps)
    • Fast-mode (400 kbps)
    • Fast-mode plus (1 Mbps)
    • High-speed mode (3.33 Mbps)
  • Glitch suppression
  • SMBus support through software
    • Clock low time-out interrupt
    • Dual slave address capability
    • Quick command capability
  • Master and slave interrupt generation
    • Master generates interrupts when a transmit or receive operation completes (or aborts due to an error)
    • Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected
  • Master with arbitration and clock synchronization, multiple-master support, and 7-bit addressing mode
  • Efficient transfers using µDMA
    • Separate channels for transmit and receive
    • Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the I2C

Quad Synchronous Serial Interface (QSSI)

QSSI is a bidirectional communications interface that converts data between parallel and serial. The QSSI module performs serial-to-parallel conversion on data received from a peripheral device and performs parallel-to-serial conversion on data transmitted to a peripheral device. The QSSI module can be configured as either a master or slave device. As a slave device, the QSSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.

The QSSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the input clock of the QSSI module. Bit rates are generated based on the input clock, and the maximum bit rate is determined by the connected peripheral.

The four QSSI modules each support the following features:

  • Four QSSI channels with advanced, bi-SSI, and quad-SSI functionality
  • Programmable interface operation for Freescale SPI or TI synchronous serial interfaces in legacy mode. Support for Freescale interface in Bi- and Quad-SSI mode.
  • Master or slave operation
  • Programmable clock bit rate and prescaler
  • Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
  • Programmable data frame size from 4 to 16 bits
  • Internal loopback test mode for diagnostic/debug testing
  • Standard FIFO-based interrupts and end-of-transmission interrupt
  • Efficient transfers using µDMA
    • Separate channels for transmit and receive
    • Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains four entries
    • Transmit single request asserted when there is space in the FIFO; burst request asserted when four or more entries are available to be written in the FIFO
    • Maskable µDMA interrupts for receive and transmit complete
  • Global alternate clock (ALTCLK) resource or system clock (SYSCLK) can be used to generate baud clock.

System Integration

A variety of standard system functions are integrated into the device, including:

  • Direct memory access (DMA) controller (see Section
  • System control and clocks including on-chip precision 16-MHz oscillator (see Section
  • Eight 32-bit timers (each timer can be configured as two 16-bit timers) (see Section
  • Lower-power battery-backed Hibernation module (see Section
  • RTC in Hibernation module
  • Two watchdog timers (see Section
    • One timer runs off the main oscillator.
    • One timer runs off the precision internal oscillator.
  • 140 GPIOs, depending on configuration (see Section
    • Highly flexible pin multiplexing allows use as GPIO or one of several peripheral functions.
    • GPIOs are independently configurable to 2-, 4-, 8-, 10-, or 12-mA drive capability.
    • Up to 4 GPIOs can have 18-mA drive capability.

Direct Memory Access (DMA)

The DMA controller is known as micro-DMA (µDMA). The µDMA controller provides a way to offload data transfer tasks from the Cortex-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The µDMA controller provides the following features:

  • Arm PrimeCell 32-channel configurable µDMA controller
  • Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes
    • Basic for simple transfer scenarios
    • Ping-pong for continuous data flow
    • Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from one request
  • Highly flexible and configurable channel operation
    • Independently configured and operated channels
    • Dedicated channels for supported on-chip modules
    • Flexible channel assignments
    • One channel each for receive and transmit path for bidirectional modules
    • Dedicated channel for software-initiated transfers
    • Per-channel configurable priority scheme
    • Optional software-initiated requests for any channel
  • Two levels of priority
  • Design optimizations for improved bus access performance between µDMA controller and the processor core
    • µDMA controller access is subordinate to core access
    • RAM striping
    • Peripheral bus segmentation
  • Data sizes of 8, 16, and 32 bits
  • Transfer size is programmable in binary steps from 1 to 1024
  • Source and destination address increment size of byte, halfword, word, or no increment
  • Maskable peripheral requests
  • Interrupt on transfer completion, with a separate interrupt per channel

Each DMA channel has up to nine possible assignments that are selected using the DMA Channel Map Select n (DMACHMAPn) registers with 4-bit assignment fields for each µDMA channel.

Table 6-2 lists the µDMA channel mapping. The Encoding column lists the encoding for the respective DMACHMAPn bit field. Encodings 0x9 to 0xF are reserved. The Type column indicates if a particular peripheral uses a single request (S), burst request (B), or either (SB).


Channels or encodings marked as Reserved cannot be used for µDMA transfers. Channels designated in the table as only "Software" are dedicated software channels. When only one software request is required in an application, dedicated software channels can be used. If multiple software requests in code are required, then peripheral channel software requests should be used for proper µDMA completion acknowledgement.

Table 6-2 µDMA Channel Assignments

Channel Encoding
0 1 2 3 4 5 6 7 8
Peripheral Type Peripheral Type Peripheral Type Peripheral Type Peripheral Type Peripheral Type Peripheral Type Peripheral Type Peripheral Type
0 Reserved UART2 RX SB Reserved GPTimer 4A B Reserved Reserved I2C0 RX SB Reserved Reserved
1 Reserved UART2 TX SB Reserved GPTimer 4B B Reserved Reserved I2C0 TX SB Reserved Reserved
2 Reserved GPTimer 3A B Reserved Reserved Reserved Reserved I2C1RX SB Reserved Reserved
3 Reserved GPTimer 3B B Reserved Software S Reserved Reserved I2C1 TX SB Reserved Reserved
4 Reserved GPTimer 2A B Reserved GPIO A B Reserved SHA/MD5 0 Cin B I2C2 RX SB Reserved Reserved
5 Reserved GPTimer 2B B Reserved GPIO B B Reserved SHA/MD5 0 Din B I2C2 TX SB Reserved Reserved
6 Reserved GPTimer 2A B UART5 RX SB GPIO C B I2C0 RX SB SHA/MD5 0 Cout B Reserved Reserved Reserved
7 Reserved GPTimer 2B B UART5 TX SB GPIO D B I2C0 TX SB Reserved Reserved Reserved Reserved
8 UART0 RX SB UART1 RX SB Reserved GPTimer 5A B I2C1RX SB Reserved Reserved Reserved Reserved
9 UART0 TX SB UART1 TX SB Reserved GPTimer 5B B I2C1 TX SB Reserved Reserved Reserved Reserved
10 SSI0 RX SB SSI1 RX SB UART6 RX SB Reserved I2C2 RX SB Reserved Reserved GPTimer 6A B Reserved
11 SSI0 TX SB SSI1 TX SB UART6 TX SB Reserved I2C2 TX SB Reserved Reserved GPTimer 6B B Reserved
12 Reserved UART2 RX SB SSI2 RX SB Reserved GPIO K B AES0 Cin B Reserved GPTimer 7A B Reserved
13 Reserved UART2 TX SB SSI2 TX SB Reserved GPIO L B AES0 Cout B Reserved GPTimer 7B B Reserved
14 ADC0 SS0 SB GPTimer 2A B SSI3 RX SB GPIO E B GPIO M B AES0 Din B Reserved Reserved Reserved
15 ADC0 SS1 SB GPTimer 2B B SSI3 TX SB GPIO F B GPIO N B AES0 Dout B Reserved Reserved Reserved
16 ADC0 SS2 SB Reserved UART3 RX SB Reserved GPIO P B Reserved Reserved Reserved Reserved
17 ADC0 SS3 SB Reserved UART3 TX SB Reserved Reserved Reserved Reserved Reserved Reserved
18 GPTimer 0A B GPTimer 1A B UART4 RX SB GPIO B B I2C3 RX SB Reserved Reserved Reserved Reserved
19 GPTimer 0B B GPTimer 1B B UART4 TX SB GPIO G B I2C3 TX SB Reserved Reserved Reserved Reserved
20 GPTimer 1A B EPI0 RX Software B UART7 RX SB GPIO H B I2C4 RX SB DES0 Cin B Reserved Reserved Reserved
21 GPTimer 1B B EPI0 TX Software B UART7 TX SB GPIO J B I2C4 TX SB DES0 Din B Reserved Reserved Reserved
22 UART1 RX SB Software B Reserved Software B I2C5 RX SB DES0 Dout B Reserved Reserved I2C8 RX B
23 UART1 TX SB Software B Reserved Software B I2C5 TX SB Reserved Reserved Reserved I2C8 TX B
24 SSI1 RX SB ADC1 SS0 SB Reserved Reserved GPIO Q B Reserved Reserved Reserved I2C9 RX B
25 SSI1 TX SB ADC1 SS1 SB Reserved Reserved GPIO R B Reserved Reserved Reserved I2C9 TX B
26 Software B ADC1 SS2 SB Reserved Reserved GPIO S B Reserved Reserved Reserved I2C6 RX B
27 Software B ADC1 SS3 SB Reserved Reserved Reserved Reserved GPIO T B Reserved I2C6 TX B
28 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved I2C7 RX B
29 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved I2C7 TX B
30 Software B Software B Reserved Software B Reserved Reserved Reserved EPI0 RX B 1Wire0 B
31 Reserved Reserved Reserved Reserved B Reserved Reserved Reserved EPI0 TX B Reserved

System Control and Clocks

System control determines the overall operation of the device. It provides information about the device, controls power-saving features, controls the clocking of the device and individual peripherals, and handles reset detection and reporting.

  • Device identification information: version, part number, SRAM size, flash memory size, and so on
  • Power control
    • On-chip fixed low dropout (LDO) voltage regulator
    • Hibernation module manages the power-up and power-down 3.3-V sequencing and control for the core digital logic and analog circuits
    • Low-power options for MCU: sleep and deep-sleep modes with clock gating
    • Low-power options for on-chip modules: software controls shutdown of individual peripherals and memory
    • 3.3-V supply brownout detection and reporting through interrupt or reset
  • Multiple clock sources for the system clock. The MCU is clocked by the system clock (SYSCLK) that is distributed to the processor and integrated peripherals after clock gating. The SYSCLK frequency is based on the frequency of the clock source and a divisor factor. A PLL is provided for the generation of system clock frequencies in excess of the reference clock provided. The reference clocks for the PLL are the PIOSC and the main crystal oscillator. The following clock sources are provided to the MCU:
    • 16-MHz precision oscillator (PIOSC)
    • Main oscillator (MOSC): A frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins.
    • Low-frequency internal oscillator (LFIOSC): On-chip resource used during power-saving modes.
    • Hibernate RTC oscillator (RTCOSC): A clock that can be configured to be the 32.768-kHz external oscillator source from the HIB module or the HIB low-frequency clock source (HIB LFIOSC), which is in the HIB module.
  • Flexible reset sources
    • Power-on reset (POR)
    • Reset pin assertion
    • Brownout reset (BOR) detector alerts to system power drops
    • Software reset
    • Watchdog timer reset
    • Hibernation module event
    • MOSC failure
  • 128-bit unique identifier for individual device identification

Programmable Timers

Programmable timers can be used to count or time external events that drive the Timer input pins. Each 16- or 32-bit General-Purpose Timer Module (GPTM) block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters. These two timers/counters can also be configured to operate as one 32-bit timer or one 32-bit RTC. Timers can also be used to trigger analog-to-digital conversions and DMA transfers.

The GPTM contains eight 16- or 32-bit GPTM blocks with the following functional options:

  • Operating modes
    • 16- or 32-bit programmable one-shot timer
    • 16- or 32-bit programmable periodic timer
    • 16-bit general-purpose timer with an 8-bit prescaler
    • 32-bit RTC when using an external 32.768-kHz clock as the input
    • 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
    • 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal
  • Count up or down
  • Sixteen 16- or 32-bit capture/compare PWM (CCP) pins
  • Daisy-chaining of timer modules lets one timer initiate multiple timing events
  • Timer synchronization lets selected timers start counting on the same clock cycle
  • ADC event trigger
  • User-enabled stalling when the MCU asserts the CPU halt flag during debug (excluding RTC mode)
  • Can determine the elapsed time between the assertion of the timer interrupt and entry into the ISR
  • Efficient transfers using µDMA
    • Dedicated channel for each timer
    • Burst request generated on timer interrupt

Capture Compare PWM (CCP) Pins

CCP pins can be used by the General-Purpose Timer module to time or count external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin.

The 16/32-bit CCP pins can be programmed to operate in the following modes:

  • Capture: The GP timer is incremented or decremented by programmed events on the CCP input. The GP timer captures and stores the current timer value when a programmed event occurs.
  • Compare: The GP timer is incremented or decremented by programmed events on the CCP input. The GP timer compares the current value with a stored value and generates an interrupt when a match occurs.
  • PWM: The GP timer is incremented or decremented by the system clock. A PWM signal is generated based on a match between the counter value and a value stored in a match register and is output on the CCP pin.

Hibernation (HIB) Module

The HIB module provides logic to switch power off to the main processor and peripherals and to wake on external or time-based events. The HIB module includes power-sequencing logic and has the following features:

  • 32-bit RTC with 1/32768-second resolution and a 15-bit subseconds counter
    • 32-bit RTC seconds match register and a 15-bit subseconds match for timed wakeup and interrupt generation with 1/32768-second resolution
    • RTC predivider trim for making fine adjustments to the clock rate
  • Hardware calendar function
    • Year, month, day, day of week, hours, minutes, and seconds
    • Four-year leap compensation
    • 24-hour or AM and PM configuration
  • Two mechanisms for power control
    • System power control using a discrete external regulator
    • On-chip power control using internal switches under register control
  • VDD supplies power when valid, even if VBAT > VDD
  • Dedicated pin for wake using an external signal
  • Can configure the external reset (RST) pin or up to four GPIO port pins as wake sources, with programmable wake level
  • Tamper functionality
    • Support for four tamper inputs
    • Configurable level, weak pullup, and glitch filter
    • Configurable tamper event response
    • Logging of up to four tamper events
    • Optional BBRAM erase on tamper detection
    • Tamper detection and wake-from-hibernate capability
    • Hibernation clock input failure detect with a switch to the internal oscillator on detection
  • RTC operational and hibernation memory valid as long as VDD or VBAT is valid
  • Low-battery detection, signaling, and interrupt generation, with optional wake on low battery
  • GPIO pin state can be retained during hibernation
  • Clock source from an internal low-frequency oscillator (HIB LFIOSC) or a 32.768-kHz external crystal or oscillator
  • Sixteen 32-bit words of battery-backed memory to save state during hibernation
  • Programmable interrupts for:
    • RTC match
    • External wake
    • Low battery

Watchdog Timers

A watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The watchdog timer can generate an interrupt, a nonmaskable interrupt, or a reset when a time-out value is reached. In addition, the watchdog timer is Arm FiRM-compliant and can be configured to generate an interrupt to the MCU on its first time-out, and to generate a reset signal on its second time-out. After the watchdog timer has been configured, the lock register can be written to prevent inadvertently altering the timer configuration.

Two watchdog timer modules are supported: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The watchdog timer module has the following features:

  • 32-bit down counter with a programmable load register
  • Separate watchdog clock with an enable
  • Programmable interrupt generation logic with interrupt masking and optional NMI function
  • Lock register protection from runaway software
  • Reset generation logic with an enable/disable
  • User-enabled stalling when the MCU asserts the CPU Halt flag during debug

Programmable GPIOs

General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The GPIO module is composed of 18 physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the Arm Foundation IP for Real-Time MCUs specification) and supports 0 to 140 programmable I/O pins. The number of GPIOs available depends on the peripherals being used.

  • Up to 140 GPIOs, depending on configuration
  • Highly flexible pin multiplexing allows use as GPIO or one of several peripheral functions
  • 3.3-V tolerant in input configuration
  • Advanced high-performance bus (AHB) accesses all ports:
    • Ports A to H, J to N, and P to T
  • Fast toggle capable of a change every clock cycle for ports on AHB
  • Programmable control for GPIO interrupts
    • Interrupt generation masking
    • Edge-triggered on rising, falling, or both
    • Level-sensitive on high or low values
    • Per-pin interrupts available on port P and port Q
  • Bit masking in both read and write operations through address lines
  • Can be used to initiate an ADC sample sequence or a µDMA transfer
  • Pin state can be retained during hibernation mode; pins on port P can be programmed to wake on level in hibernation mode
  • Pins configured as digital inputs are Schmitt triggered
  • Programmable control for GPIO pad configuration
    • Weak pullup or pulldown resistors
    • 2-, 4-, 6-, 8-, 10-, or 12-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications
    • Slew rate control for 8-, 10-, and 12-mA pad drive
    • Open-drain enables
    • Digital-input enables

LCD Controller

The LCD controller supports the following features:

  • Character-based panels
    • Support for two character panels (CS0 and CS1) with independent and programmable bus timing parameters when in asynchronous Hitachi, Motorola, and Intel modes
    • Support for one character panel (CS0) with programmable bus timing parameters when in synchronous Motorola and Intel modes
    • Can be used as a generic 16-bit address and data interleaved MPU bus master with no external stall
  • Passive matrix LCD panels
    • Panel types including STN, DSTN, and C-DSTN
    • AC Bias Control
  • Active matrix LCD panels
    • Panel types including TN TFT
    • 1, 2, 4, or 8 bits per pixel with palette RAM and 16 or 24 bits per pixel without palette RAM
  • OLED panels
    • Passive matrix (PM OLED) with frame buffer and controller IC inside the panel
    • Active matrix (AM OLED)
  • Bus mastering from either system SRAM or EPI memory

Advanced Motion Control

The motion control functions that are integrated into the device support the following features:

  • Eight advanced PWM outputs for motion and energy applications
  • Four fault inputs to promote low-latency shutdown
  • One quadrature encoder input (QEI)

The following sections provides more detail on these motion control functions.

Pulse Width Modulation (PWM)

PWM is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control.

One PWM module is included, with four PWM generator blocks and a control block, for a total of eight PWM outputs. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt or ADC-trigger selector.

Each PWM generator block produces two PWM signals that can be either independent signals or a pair of complementary signals with dead-band delays inserted.

Each PWM generator has the following features:

  • Four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled
  • One 16-bit counter
    • Runs in down or up/down mode
    • Output frequency controlled by a 16-bit load value
    • Synchronized load value updates
    • Produces output signals at zero and load value
  • Two PWM comparators
    • Synchronized comparator value updates
    • Produces output signals on match
  • PWM signal generator
    • Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals.
    • Produces two independent PWM signals
  • Dead-band generator
    • Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge
    • Can be bypassed, leaving input PWM signals unmodified
  • Can initiate an ADC sample sequence

The control block determines the polarity of the PWM signals and which signals are passed through to the pins. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. The PWM control block has the following options:

  • PWM output enable of each PWM signal
  • Optional output inversion of each PWM signal (polarity control)
  • Optional fault handling for each PWM signal
  • Synchronization of timers in the PWM generator blocks
  • Synchronization of timer/comparator updates across the PWM generator blocks
  • Extended PWM synchronization of timer/comparator updates across the PWM generator blocks
  • Interrupt status summary of the PWM generator blocks
  • Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering
  • PWM generators can be operated independently or synchronized with other generators

Quadrature Encoder With Index (QEI) Module

A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index signal, can be used to reset the position counter. The QEI module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the system frequency (for example, 30 MHz for a 120-MHz system).

One QEI module provides control of one motor with the following features:

  • Position integrator that tracks the encoder position
  • Programmable noise filter on the inputs
  • Velocity capture using built-in timer
  • The input frequency of the QEI inputs may be as high as 1/4 of the system frequency (for example, 12.5 MHz for a 50-MHz system)
  • Interrupt generation on:
    • Index pulse
    • Velocity-timer expiration
    • Direction change
    • Quadrature error detection


Integrated analog functions include:

  • Two 12-bit ADCs with a total of 24 analog input channels and each with a sample rate of 2 Msps (see Section
  • Three analog comparators (see Section
  • On-chip voltage regulator


An ADC is a peripheral that converts a continuous analog voltage to a discrete digital number. The ADC module features 12-bit conversion resolution and supports 24 input channels plus an internal temperature sensor. Four buffered sample sequencers allow rapid sampling of up to 24 analog input sources without controller intervention. Each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator function that lets the conversion value be sent to a comparison unit that provides eight digital comparators.

Both ADC modules support the following features:

  • 24 shared analog input channels
  • 12-bit precision ADC
  • Single-ended and differential-input configurations
  • On-chip internal temperature sensor
  • Maximum sample rate of two million samples/second
  • Optional, programmable phase delay
  • Sample and hold window programmability
  • Four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result FIFOs
  • Flexible trigger control
    • Controller (software)
    • Timers
    • Analog comparators
    • PWM
    • GPIO
  • Hardware averaging of up to 64 samples
  • Eight digital comparators
  • Converter uses two external reference signals (VREFA+ and VREFA–) or VDDA and GNDA as the voltage reference
  • Power and ground for the analog circuitry is separate from the digital power and ground
  • Efficient transfers using µDMA
    • Dedicated channel for each sample sequencer
    • ADC module uses burst requests for DMA
  • Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate ADC clock.

Analog Comparators

An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The independent integrated analog comparators can be configured to drive an output or generate an interrupt or ADC event.

The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge.

Each analog comparator supports the following functions:

  • Compare external pin input to external pin input or to internal programmable voltage reference
  • Compare a test voltage against any one of the following voltages:
    • An individual external reference voltage
    • A shared single external reference voltage
    • A shared internal reference voltage

JTAG and Arm Serial Wire Debug

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port (TAP) and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Register (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. TI replaces the Arm SW-DP and JTAG-DP with the Arm Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. This module provides the standard JTAG debug and test functionality plus real-time access to system memory without halting the core or requiring any target resident code. The SWJ-DP interface has the following features:

  • IEEE 1149.1-1990 compatible TAP controller
  • Four-bit IR chain for storing JTAG instructions
  • IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST
  • Arm additional instructions: APACC, DPACC, and ABORT
  • Integrated Arm Serial Wire Debug (SWD)
    • Serial Wire JTAG Debug Port (SWJ-DP)
    • Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
    • Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling
    • Instrumentation Trace Macrocell (ITM) for support of printf-style debugging
    • Embedded Trace Macrocell (ETM) for instruction trace capture
    • Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

Peripheral Memory Map

Table 6-3 lists the address for each peripheral.


Within the memory map, attempts to read or write addresses in reserved spaces result in a bus fault. In addition, attempts to write addresses in the flash range also result in a bus fault.

Table 6-3 Memory Map

0x4000.0000 0x4000.0FFF Watchdog Timer 0 Table 6-34
0x4000.1000 0x4000.1FFF Watchdog Timer 1 Table 6-34
0x4000.2000 0x4000.3FFF Reserved
0x4000.4000 0x4000.4FFF GPIO Port A Table 6-18
0x4000.5000 0x4000.5FFF GPIO Port B Table 6-18
0x4000.6000 0x4000.6FFF GPIO Port C Table 6-18
0x4000.7000 0x4000.7FFF GPIO Port D Table 6-18
0x4000.8000 0x4000.8FFF SSI0 Table 6-27
0x4000.9000 0x4000.9FFF SSI1 Table 6-27
0x4000.A000 0x4000.AFFF SSI2 Table 6-27
0x4000.B000 0x4000.BFFF SSI3 Table 6-27
0x4000.C000 0x4000.CFFF UART0 Table 6-32
0x4000.D000 0x4000.DFFF UART1 Table 6-32
0x4000.E000 0x4000.EFFF UART2 Table 6-32
0x4000.F000 0x4000.FFFF UART3 Table 6-32
0x4001.0000 0x4001.0FFF UART4 Table 6-32
0x4001.1000 0x4001.1FFF UART5 Table 6-32
0x4001.2000 0x4001.2FFF UART6 Table 6-32
0x4001.3000 0x4001.3FFF UART7 Table 6-32
0x4001.4000 0x4001.FFFF Reserved
0x4002.0000 0x4002.0FFF I2C 0 Table 6-21
0x4002.1000 0x4002.1FFF I2C 1 Table 6-21
0x4002.2000 0x4002.2FFF I2C 2 Table 6-21
0x4002.3000 0x4002.3FFF I2C 3 Table 6-21
0x4002.4000 0x4002.4FFF GPIO Port E Table 6-18
0x4002.5000 0x4002.5FFF GPIO Port F Table 6-18
0x4002.6000 0x4002.6FFF GPIO Port G Table 6-18
0x4002.7000 0x4002.7FFF GPIO Port H Table 6-18
0x4002.8000 0x4002.8FFF PWM 0 Table 6-25
0x4002.9000 0x4002.BFFF Reserved
0x4002.C000 0x4002.CFFF QEI0 Table 6-26
0x4002.D000 0x4002.FFFF Reserved
0x4003.0000 0x4003.0FFF 16/32-bit Timer 0 Table 6-19
0x4003.1000 0x4003.1FFF 16/32-bit Timer 1 Table 6-19
0x4003.2000 0x4003.2FFF 16/32-bit Timer 2 Table 6-19
0x4003.3000 0x4003.3FFF 16/32-bit Timer 3 Table 6-19
0x4003.4000 0x4003.4FFF 16/32-bit Timer 4 Table 6-19
0x4003.5000 0x4003.5FFF 16/32-bit Timer 5 Table 6-19
0x4003.6000 0x4003.7FFF Reserved
0x4003.8000 0x4003.8FFF ADC0 Table 6-7
0x4003.9000 0x4003.9FFF ADC1 Table 6-7
0x4003.A000 0x4003.BFFF Reserved
0x4003.C000 0x4003.CFFF Analog Comparator Table 6-9
0x4003.D000 0x4003.DFFF GPIO Port J Table 6-18
0x4003.E000 0x4003.FFFF Reserved
0x4004.0000 0x4004.0FFF CAN0 Controller Table 6-8
0x4004.1000 0x4004.1FFF CAN1 Controller Table 6-8
0x4004.2000 0x4004.FFFF Reserved
0x4005.0000 0x4005.0FFF USB Table 6-33
0x4005.1000 0x4005.7FFF Reserved
0x4005.8000 0x4005.8FFF GPIO Port A (AHB aperture) Table 6-18
0x4005.9000 0x4005.9FFF GPIO Port B (AHB aperture) Table 6-18
0x4005.A000 0x4005.AFFF GPIO Port C (AHB aperture) Table 6-18
0x4005.B000 0x4005.BFFF GPIO Port D (AHB aperture) Table 6-18
0x4005.C000 0x4005.CFFF GPIO Port E (AHB aperture) Table 6-18
0x4005.D000 0x4005.DFFF GPIO Port F (AHB aperture) Table 6-18
0x4005.E000 0x4005.EFFF GPIO Port G (AHB aperture) Table 6-18
0x4005.F000 0x4005.FFFF GPIO Port H (AHB aperture) Table 6-18
0x4006.0000 0x4006.0FFF GPIO Port J (AHB aperture) Table 6-18
0x4006.1000 0x4006.1FFF GPIO Port K (AHB aperture) Table 6-18
0x4006.2000 0x4006.2FFF GPIO Port L (AHB aperture) Table 6-18
0x4006.3000 0x4006.3FFF GPIO Port M (AHB aperture) Table 6-18
0x4006.4000 0x4006.4FFF GPIO Port N (AHB aperture) Table 6-18
0x4006.5000 0x4006.5FFF GPIO Port P (AHB aperture) Table 6-18
0x4006.6000 0x4006.6FFF GPIO Port Q (AHB aperture) Table 6-18
0x4006.7000 0x4006.7FFF GPIO Port R (AHB aperture) Table 6-18
0x4006.8000 0x4006.8FFF GPIO Port S (AHB aperture) Table 6-18
0x4006.9000 0x4006.9FFF GPIO Port T (AHB aperture) Table 6-18
0x4006.A000 0x400A.EFFF Reserved
0x400A.F000 0x400A.FFFF EEPROM and Key Locker Table 6-13
0x400B.0000 0x400B.5FFF Reserved
0x400B.6000 0x400B.6FFF 1-Wire Master Table 6-4
0x400B.7000 0x400B.7FFF Reserved
0x400B.8000 0x400B.8FFF I2C 8 Table 6-21
0x400B.9000 0x400B.9FFF I2C 9 Table 6-21
0x400B.A000 0x400B.FFFF Reserved
0x400C.0000 0x400C.0FFF I2C 4 Table 6-21
0x400C.1000 0x400C.1FFF I2C 5 Table 6-21
0x400C.2000 0x400C.2FFF I2C 6 Table 6-21
0x400C.3000 0x400C.3FFF I2C 7 Table 6-21
0x400C.4000 0x400C.FFFF Reserved
0x400D.0000 0x400D.0FFF EPI0 Table 6-14
0x400D.1000 0x400D.FFFF Reserved
0x400E.0000 0x400E.0FFF 16/32-bit Timer 6 Table 6-19
0x400E.1000 0x400E.1FFF 16/32-bit Timer 7 Table 6-19
0x400E.2000 0x400E.BFFF Reserved
0x400E.C000 0x400E.CFFF Ethernet Controller Table 6-15
0x400E.D000 0x400F.8FFF Reserved
0x400F.9000 0x400F.9FFF System Exception Table 6-31
0x400F.A000 0x400F.BFFF Reserved
0x400F.C000 0x400F.CFFF Hibernation Table 6-20
0x400F.D000 0x400F.DFFF Flash Memory Control Table 6-17
0x400F.E000 0x400F.EFFF System Control Table 6-30
0x400F.F000 0x400F.FFFF µDMA Table 6-23
0x4010.0000 0x41FF.FFFF Reserved
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
0x4400.0000 0x4402.FFFF Reserved
0x4403.0000 0x4403.0FFF CRC and Cryptographic Control Table 6-10
0x4403.1000 0x4403.1FFF Reserved (4KB)
0x4403.2000 0x4403.3FFF Reserved (8KB)
0x4403.4000 0x4403.5FFF SHA/MD5 Table 6-28
0x4403.6000 0x4403.7FFF AES Table 6-5, Table 6-6
0x4403.8000 0x4403.9FFF DES Table 6-11, Table 6-12
0x4403.A000 0x4403.EFFF Reserved
0x4403.F000 0x4403.FFFF Reserved (4KB)
0x4404.0000 0x4404.FFFF Reserved (64KB)
0x4405.0000 0x4405.0FFF LCD Table 6-22
0x4405.1000 0x4405.3FFF Reserved
0x4405.4000 0x4405.4FFF EPHY 0 Table 6-16
0x4405.5000 0x5FFF.FFFF Reserved
0x6000.0000 0xDFFF.FFFF EPI0 Mapped Peripheral and RAM Table 6-14

Table 6-4 1-Wire Master Registers

0x0 ONEWIRECS 1-Wire Control and Status
0x4 ONEWIRETIM 1-Wire Timing Override
0x8 ONEWIREDATW 1-Wire Data Write
0xC ONEWIREDATR 1-Wire Data Read
0x100 ONEWIREIM 1-Wire Interrupt Mask
0x104 ONEWIRERIS 1-Wire Raw Interrupt Status
0x108 ONEWIREMIS 1-Wire Masked Interrupt Status
0x10C ONEWIREICR 1-Wire Interrupt Clear
0x120 ONEWIREDMA 1-Wire µDMA Control
0xFC0 ONEWIREPP 1-Wire Peripheral Properties

Table 6-5 AES Registers

0x00C AES_KEY2_5 AES Key 2_5
0x010 AES_KEY2_2 AES Key 2_2
0x014 AES_KEY2_3 AES Key 2_3
0x018 AES_KEY2_0 AES Key 2_0
0x01C AES_KEY2_1 AES Key 2_1
0x020 AES_KEY1_6 AES Key 1_6
0x024 AES_KEY1_7 AES Key 1_7
0x028 AES_KEY1_4 AES Key 1_4
0x02C AES_KEY1_5 AES Key 1_5
0x030 AES_KEY1_2 AES Key 1_2
0x034 AES_KEY1_3 AES Key 1_3
0x038 AES_KEY1_0 AES Key 1_0
0x03C AES_KEY1_1 AES Key 1_1
0x40 to 0x4C AES_IV_IN_0 to AES_IV_IN_3 AES Initialization Vector Input 0 to AES Initialization Vector Input 3
0x50 AES_CTRL AES Control
0x54 to 0x58 AES_C_LENGTH_0 to AES_C_LENGTH_1 AES Crypto Data Length 0 to AES Crypto Data Length 1
0x5C AES_AUTH_LENGTH AES Authentication Data Length
0x60 to 0x6C AES_DATA_IN_0 to AES_DATA_IN_3 AES Data R/W Plaintext/Ciphertext 0 to AES Data R/W Plaintext/Ciphertext 3
0x70 to 0x7C AES_TAG_OUT_0 to AES_TAG_OUT_3 AES Hash Tag Out 0 to AES Hash Tag Out 3
0x80 AES_REVISION AES IP Revision Identifier
0x84 AES_SYSCONFIG AES System Configuration
0x88 AES_SYSSTATUS AES System Status
0x8C AES_IRQSTATUS AES Interrupt Status
0x90 AES_IRQENABLE AES Interrupt Enable

Table 6-6 AES µDMA Registers

0x20 AES_DMAIM AES DMA Interrupt Mask
0x24 AES_DMARIS AES DMA Raw Interrupt Status
0x28 AES_DMAMIS AES DMA Masked Interrupt Status
0x2C AES_DMAIC AES DMA Interrupt Clear

Table 6-7 ADC Registers

0x0 ADCACTSS ADC Active Sample Sequencer
0x4 ADCRIS ADC Raw Interrupt Status
0x8 ADCIM ADC Interrupt Mask
0xC ADCISC ADC Interrupt Status and Clear
0x10 ADCOSTAT ADC Overflow Status
0x14 ADCEMUX ADC Event Multiplexer Select
0x18 ADCUSTAT ADC Underflow Status
0x1C ADCTSSEL ADC Trigger Source Select
0x20 ADCSSPRI ADC Sample Sequencer Priority
0x24 ADCSPC ADC Sample Phase Control
0x28 ADCPSSI ADC Processor Sample Sequence Initiate
0x30 ADCSAC ADC Sample Averaging Control
0x34 ADCDCISC ADC Digital Comparator Interrupt Status and Clear
0x38 ADCCTL ADC Control
0x40 ADCSSMUX0 ADC Sample Sequence Input Multiplexer Select 0
0x44 ADCSSCTL0 ADC Sample Sequence Control 0
0x48 ADCSSFIFO0 ADC Sample Sequence Result FIFO 0
0x4C ADCSSFSTAT0 ADC Sample Sequence FIFO 0 Status
0x50 ADCSSOP0 ADC Sample Sequence 0 Operation
0x54 ADCSSDC0 ADC Sample Sequence 0 Digital Comparator Select
0x58 ADCSSEMUX0 ADC Sample Sequence Extended Input Multiplexer Select 0
0x5C ADCSSTSH0 ADC Sample Sequence 0 Sample and Hold Time
0x60 ADCSSMUX1 ADC Sample Sequence Input Multiplexer Select 1
0x64 ADCSSCTL1 ADC Sample Sequence Control 1
0x068 ADCSSFIFO1 ADC Sample Sequence Result FIFO 1
0x06C ADCSSFSTAT1 ADC Sample Sequence FIFO 1 Status
0x70 ADCSSOP1 ADC Sample Sequence 1 Operation
0x74 ADCSSDC1 ADC Sample Sequence 1 Digital Comparator Select
0x78 ADCSSEMUX1 ADC Sample Sequence Extended Input Multiplexer Select 1
0x7C ADCSSTSH1 ADC Sample Sequence 1 Sample and Hold Time
0x080 ADCSSMUX2 ADC Sample Sequence Input Multiplexer Select 2
0x084 ADCSSCTL2 ADC Sample Sequence Control 2
0x088 ADCSSFIFO2 ADC Sample Sequence Result FIFO 2
0x08C ADCSSFSTAT2 ADC Sample Sequence FIFO 2 Status
0x090 ADCSSOP2 ADC Sample Sequence 2 Operation
0x094 ADCSSDC2 ADC Sample Sequence 2 Digital Comparator Select
0x098 ADCSSEMUX2 ADC Sample Sequence Extended Input Multiplexer Select 2
0x09C ADCSSTSH2 ADC Sample Sequence 2 Sample and Hold Time
0xA0 ADCSSMUX3 ADC Sample Sequence Input Multiplexer Select 3
0xA4 ADCSSCTL3 ADC Sample Sequence Control 3
0x0A8 ADCSSFIFO3 ADC Sample Sequence Result FIFO 3
0x0AC ADCSSFSTAT3 ADC Sample Sequence FIFO 3 Status
0xB0 ADCSSOP3 ADC Sample Sequence 3 Operation
0xB4 ADCSSDC3 ADC Sample Sequence 3 Digital Comparator Select
0xB8 ADCSSEMUX3 ADC Sample Sequence Extended Input Multiplexer Select 3
0xBC ADCSSTSH3 ADC Sample Sequence 3 Sample and Hold Time
0xD00 ADCDCRIC ADC Digital Comparator Reset Initial Conditions
0xE00 to 0xE1C ADCDCCTL0 to ADCDCCTL7 ADC Digital Comparator Control 0 to ADC Digital Comparator Control 7
0xE40 to 0xE5C ADCDCCMP0 to ADCDCCMP7 ADC Digital Comparator Range 0 to ADC Digital Comparator Range 7
0xFC0 ADCPP ADC Peripheral Properties
0xFC4 ADCPC ADC Peripheral Configuration
0xFC8 ADCCC ADC Clock Configuration

Table 6-8 CAN Registers

0x0 CANCTL CAN Control
0x4 CANSTS CAN Status
0x8 CANERR CAN Error Counter
0xC CANBIT CAN Bit Timing
0x10 CANINT CAN Interrupt
0x14 CANTST CAN Test
0x18 CANBRPE CAN Baud Rate Prescaler Extension
0x20 CANIF1CRQ CAN IF1 Command Request
0x24 CANIF1CMSK CAN IF1 Command Mask
0x28 CANIF1MSK1 CAN IF1 Mask 1
0x2C CANIF1MSK2 CAN IF1 Mask 2
0x30 CANIF1ARB1 CAN IF1 Arbitration 1
0x34 CANIF1ARB2 CAN IF1 Arbitration 2
0x38 CANIF1MCTL CAN IF1 Message Control
0x3C CANIF1DA1 CAN IF1 Data A1
0x40 CANIF1DA2 CAN IF1 Data A2
0x44 CANIF1DB1 CAN IF1 Data B1
0x48 CANIF1DB2 CAN IF1 Data B2
0x80 CANIF2CRQ CAN IF2 Command Request
0x84 CANIF2CMSK CAN IF2 Command Mask
0x88 CANIF2MSK1 CAN IF2 Mask 1
0x8C CANIF2MSK2 CAN IF2 Mask 2
0x90 CANIF2ARB1 CAN IF2 Arbitration 1
0x94 CANIF2ARB2 CAN IF2 Arbitration 2
0x98 CANIF2MCTL CAN IF2 Message Control
0x9C CANIF2DA1 CAN IF2 Data A1
0xA0 CANIF2DA2 CAN IF2 Data A2
0xA4 CANIF2DB1 CAN IF2 Data B1
0xA8 CANIF2DB2 CAN IF2 Data B2
0x100 CANTXRQ1 CAN Transmission Request 1
0x104 CANTXRQ2 CAN Transmission Request 2
0x120 CANNWDA1 CAN New Data 1
0x124 CANNWDA2 CAN New Data 2
0x140 CANMSG1INT CAN Message 1 Interrupt Pending
0x144 CANMSG2INT CAN Message 2 Interrupt Pending
0x160 CANMSG1VAL CAN Message 1 Valid
0x164 CANMSG2VAL CAN Message 2 Valid

Table 6-9 Comparator Registers

0x0 ACMIS Analog Comparator Masked Interrupt Status
0x4 ACRIS Analog Comparator Raw Interrupt Status
0x8 ACINTEN Analog Comparator Interrupt Enable
0x10 ACREFCTL Analog Comparator Reference Voltage Control
0x20 ACSTAT0 Analog Comparator Status 0
0x24 ACCTL0 Analog Comparator Control 0
0x40 ACSTAT1 Analog Comparator Status 1
0x44 ACCTL1 Analog Comparator Control 1
0x60 ACSTAT2 Analog Comparator Status 2
0x64 ACCTL2 Analog Comparator Control 2
0xFC0 ACMPPP Analog Comparator Peripheral Properties

Table 6-10 CRC Registers

400h CRCCTRL CRC Control
414h CRCDIN CRC Data Input
418h CRCRSLTPP CRC Post Processing Result

Table 6-11 DES Registers

0x00 DES_KEY3_L DES Key 3 LSW for 192-Bit Key
0x04 DES_KEY3_H DES Key 3 MSW for 192-Bit Key
0x08 DES_KEY2_L DES Key 2 LSW for 128-Bit Key
0x0C DES_KEY2_H DES Key 2 MSW for 128-Bit Key
0x10 DES_KEY1_L DES Key 1 LSW for 64-Bit Key
0x14 DES_KEY1_H DES Key 1 MSW for 64-Bit Key
0x18 DES_IV_L DES Initialization Vector
0x1C DES_IV_H DES Initialization Vector
0x20 DES_CTRL DES Control
0x24 DES_LENGTH DES Cryptographic Data Length
0x30 DES_REVISION DES Revision Number
0x34 DES_SYSCONFIG DES System Configuration
0x38 DES_SYSSTATUS DES System Status
0x3C DES_IRQSTATUS DES Interrupt Status
0x40 DES_IRQENABLE DES Interrupt Enable

Table 6-12 DES µDMA Registers

0x30 DES_DMAIM DES DMA Interrupt Mask
0x34 DES_DMARIS DES DMA Raw Interrupt Status
0x38 DES_DMAMIS DES DMA Masked Interrupt Status
0x3C DES_DMAIC DES DMA Interrupt Clear

Table 6-13 EEPROM Registers

0x0 EESIZE EEPROM Size Information
0x4 EEBLOCK EEPROM Current Block
0x8 EEOFFSET EEPROM Current Offset
0x10 EERDWR EEPROM Read-Write
0x14 EERDWRINC EEPROM Read-Write with Increment
0x18 EEDONE EEPROM Done Status
0x1C EESUPP EEPROM Support Control and Status
0x30 EEPROT EEPROM Protection
0x34 to 0x3C EEPASS0 to EEPASS2 EEPROM Password 0 to EEPROM Password 2
0x40 EEINT EEPROM Interrupt
0x50 EEHIDE0 EEPROM Block Hide 0
0x54 EEHIDE1 EEPROM Block Hide 1
0x58 EEHIDE2 EEPROM Block Hide 2
0x80 EEDBGME EEPROM Debug Mass Erase
0xFC0 EEPROMPP EEPROM Peripheral Properties

Table 6-14 EPI Registers

0x000 EPICFG EPI Configuration
0x004 EPIBAUD EPI Main Baud Rate
0x008 EPIBAUD2 EPI Main Baud Rate
0x010 EPISDRAMCFG EPI SDRAM Configuration
0x010 EPIHB8CFG EPI Host-Bus 8 Configuration
0x010 EPIHB16CFG EPI Host-Bus 16 Configuration
0x010 EPIGPCFG EPI General-Purpose Configuration
0x014 EPIHB8CFG2 EPI Host-Bus 8 Configuration 2
0x014 EPIHB16CFG2 EPI Host-Bus 16 Configuration 2
0x01C EPIADDRMAP EPI Address Map
0x020 EPIRSIZE0 EPI Read Size 0
0x024 EPIRADDR0 EPI Read Address 0
0x028 EPIRPSTD0 EPI Non-Blocking Read Data 0
0x030 EPIRSIZE1 EPI Read Size 1
0x034 EPIRADDR1 EPI Read Address 1
0x038 EPIRPSTD1 EPI Non-Blocking Read Data 1
0x060 EPISTAT EPI Status
0x200 EPIFIFOLVL EPI FIFO Level Selects
0x28 EPIDMATXCNT EPI DMA Transmit Count
0x210 EPIIM EPI Interrupt Mask
0x214 EPIRIS EPI Raw Interrupt Status
0x218 EPIMIS EPI Masked Interrupt Status
0x21C EPIEISC EPI Error and Interrupt Status and Clear
0x308 EPIHB8CFG3 EPI Host-Bus 8 Configuration 3
0x308 EPIHB16CFG3 EPI Host-Bus 16 Configuration 3
0x30C EPIHB8CFG4 EPI Host-Bus 8 Configuration 4
0x30C EPIHB16CFG4 EPI Host-Bus 16 Configuration 4
0x310 EPIHB8TIME EPI Host-Bus 8 Timing Extension
0x310 EPIHB16TIME EPI Host-Bus 16 Timing Extension
0x314 EPIHB8TIME2 EPI Host-Bus 8 Timing Extension
0x314 EPIHB16TIME2 EPI Host-Bus 16 Timing Extension
0x318 EPIHB8TIME3 EPI Host-Bus 8 Timing Extension
0x318 EPIHB16TIME3 EPI Host-Bus 16 Timing Extension
0x31C EPIHB8TIME4 EPI Host-Bus 8 Timing Extension
0x31C EPIHB16TIME4 EPI Host-Bus 16 Timing Extension

Table 6-15 Ethernet MAC (EMAC) Registers

0x0 EMACCFG Ethernet MAC Configuration
0x4 EMACFRAMEFLTR Ethernet MAC Frame Filter
0x8 EMACHASHTBLH Ethernet MAC Hash Table High
0xC EMACHASHTBLL Ethernet MAC Hash Table Low
0x10 EMACMIIADDR Ethernet MAC MII Address
0x14 EMACMIIDATA Ethernet MAC MII Data Register
0x18 EMACFLOWCTL Ethernet MAC Flow Control
0x24 EMACSTATUS Ethernet MAC Status
0x28 EMACRWUFF Ethernet MAC Remote Wake-Up Frame Filter
0x2C EMACPMTCTLSTAT Ethernet MAC PMT Control and Status
0x30 EMACLPICTLSTAT LPI Control and Status
0x38 EMACRIS Ethernet MAC Raw Interrupt Status
0x3C EMACIM Ethernet MAC Interrupt Mask
0x40 EMACADDR0H Ethernet MAC Address 0 High
0x44 EMACADDR0L Ethernet MAC Address 0 Low Register
0x48 EMACADDR1H Ethernet MAC Address 1 High
0x4C EMACADDR1L Ethernet MAC Address 1 Low
0x50 EMACADDR2H Ethernet MAC Address 2 High
0x54 EMACADDR2L Ethernet MAC Address 2 Low
0x58 EMACADDR3H Ethernet MAC Address 3 High
0x5C EMACADDR3L Ethernet MAC Address 3 Low
0xDC EMACWDOGTO Ethernet MAC Watchdog Time-out
0x100 EMACMMCCTRL Ethernet MAC MMC Control
0x104 EMACMMCRXRIS Ethernet MAC MMC Receive Raw Interrupt Status
0x108 EMACMMCTXRIS Ethernet MAC MMC Transmit Raw Interrupt Status
0x10C EMACMMCRXIM Ethernet MAC MMC Receive Interrupt Mask
0x110 EMACMMCTXIM Ethernet MAC MMC Transmit Interrupt Mask
0x118 EMACTXCNTGB Ethernet MAC Transmit Frame Count for Good and Bad Frames
0x14C EMACTXCNTSCOL Ethernet MAC Transmit Frame Count for Frames Transmitted After Single Collision
0x150 EMACTXCNTMCOL Ethernet MAC Transmit Frame Count for Frames Transmitted After Multiple Collisions
0x164 EMACTXOCTCNTG Ethernet MAC Transmit Octet Count Good
0x180 EMACRXCNTGB Ethernet MAC Receive Frame Count for Good and Bad Frames
0x194 EMACRXCNTCRCERR Ethernet MAC Receive Frame Count for CRC Error Frames
0x198 EMACRXCNTALGNERR Ethernet MAC Receive Frame Count for Alignment Error Frames
0x1C4 EMACRXCNTGUNI Ethernet MAC Receive Frame Count for Good Unicast Frames
0x584 EMACVLNINCREP Ethernet MAC VLAN Tag Inclusion or Replacement
0x588 EMACVLANHASH Ethernet MAC VLAN Hash Table
0x700 EMACTIMSTCTRL Ethernet MAC Timestamp Control
0x704 EMACSUBSECINC Ethernet MAC Sub-Second Increment
0x708 EMACTIMSEC Ethernet MAC System Time - Seconds
0x70C EMACTIMNANO Ethernet MAC System Time - Nanoseconds
0x710 EMACTIMSECU Ethernet MAC System Time - Seconds Update
0x714 EMACTIMNANOU Ethernet MAC System Time - Nanoseconds Update
0x718 EMACTIMADD Ethernet MAC Timestamp Addend
0x71C EMACTARGSEC Ethernet MAC Target Time Seconds
0x720 EMACTARGNANO Ethernet MAC Target Time Nanoseconds
0x724 EMACHWORDSEC Ethernet MAC System Time-Higher Word Seconds
0x728 EMACTIMSTAT Ethernet MAC Timestamp Status
0x72C EMACPPSCTRL Ethernet MAC PPS Control
0x760 EMACPPS0INTVL Ethernet MAC PPS0 Interval
0x764 EMACPPS0WIDTH Ethernet MAC PPS0 Width
0xC04 EMACTXPOLLD Ethernet MAC Transmit Poll Demand
0xC08 EMACRXPOLLD Ethernet MAC Receive Poll Demand
0xC0C EMACRXDLADDR Ethernet MAC Receive Descriptor List Address
0xC10 EMACTXDLADDR Ethernet MAC Transmit Descriptor List Address
0xC14 EMACDMARIS Ethernet MAC DMA Interrupt Status
0xC18 EMACDMAOPMODE Ethernet MAC DMA Operation Mode
0xC1C EMACDMAIM Ethernet MAC DMA Interrupt Mask Register
0xC20 EMACMFBOC Ethernet MAC Missed Frame and Buffer Overflow Counter
0xC24 EMACRXINTWDT Ethernet MAC Receive Interrupt Watchdog Timer
0xC48 EMACHOSTXDESC Ethernet MAC Current Host Transmit Descriptor
0xC4C EMACHOSRXDESC Ethernet MAC Current Host Receive Descriptor
0xC50 EMACHOSTXBA Ethernet MAC Current Host Transmit Buffer Address
0xC54 EMACHOSRXBA Ethernet MAC Current Host Receive Buffer Address
0xFC0 EMACPP Ethernet MAC Peripheral Property Register
0xFC4 EMACPC Ethernet MAC Peripheral Configuration
0xFC8 EMACCC Ethernet MAC Clock Configuration
0xFD0 EPHYRIS Ethernet PHY Raw Interrupt Status
0xFD4 EPHYIM Ethernet PHY Interrupt Mask
0xFD8 EPHYMISC Ethernet PHY Masked Interrupt Status and Clear

Table 6-16 Ethernet MII Management (EPHY) Registers (Accessed Through the EMACMIIADDR Register)

0x00 EPHYBMCR Ethernet PHY Basic Mode Control - MR0
0x01 EPHYBMSR Ethernet PHY Basic Mode Status - MR1
0x02 EPHYID1 Ethernet PHY Identifier Register 1 - MR2
0x03 EPHYID2 Ethernet PHY Identifier Register 2 - MR3
0x04 EPHYANA Ethernet PHY Auto-Negotiation Advertisement - MR4
0x05 EPHYANLPA Ethernet PHY Auto-Negotiation Link Partner Ability -MR5
0x06 EPHYANER Ethernet PHY Auto-Negotiation Expansion - MR6
0x07 EPHYANNPTR Ethernet PHY Auto-Negotiation Next Page TX - MR7
0x08 EPHYANLNPTR Ethernet PHY Auto-Negotiation Link Partner Ability Next Page - MR8
0x09 EPHYCFG1 Ethernet PHY Configuration 1 - MR9
0x0A EPHYCFG2 Ethernet PHY Configuration 2 - MR10
0x0B EPHYCFG3 Ethernet PHY Configuration 3 - MR11
0x0D EPHYREGCTL Ethernet PHY Register Control - MR13
0x0E EPHYADDAR Ethernet PHY Address or Data - MR14
0x10 EPHYSTS Ethernet PHY Status - MR16
0x11 EPHYSCR Ethernet PHY Specific Control - MR17
0x12 EPHYMISR1 Ethernet PHY MII Interrupt Status 1 - MR18
0x13 EPHYMISR2 Ethernet PHY MII Interrupt Status 2 - MR19
0x14 EPHYFCSCR Ethernet PHY False Carrier Sense Counter - MR20
0x15 EPHYRXERCNT Ethernet PHY Receive Error Count - MR21
0x16 EPHYBISTCR Ethernet PHY BIST Control - MR22
0x18 EPHYLEDCR Ethernet PHY LED Control - MR24
0x19 EPHYCTL Ethernet PHY Control - MR25
0x1A EPHY10BTSC Ethernet PHY 10Base-T Status/Control - MR26
0x1B EPHYBICSR1 Ethernet PHY BIST Control and Status 1 - MR27
0x1C EPHYBICSR2 Ethernet PHY BIST Control and Status 2 - MR28
0x1E EPHYCDCR Ethernet PHY Cable Diagnostic Control - MR30
0x1F EPHYRCR Ethernet PHY Reset Control - MR31
0x25 EPHYLEDCFG Ethernet PHY LED Configuration - MR37

Table 6-17 Flash Registers

0x0 FMA Flash Memory Address
0x4 FMD Flash Memory Data
0x8 FMC Flash Memory Control
0xC FCRIS Flash Controller Raw Interrupt Status
0x10 FCIM Flash Controller Interrupt Mask
0x14 FCMISC Flash Controller Masked Interrupt Status and Clear
0x20 FMC2 Flash Memory Control 2
0x30 FWBVAL Flash Write Buffer Valid
0x3C FLPEKEY Flash Program/Erase Key
0x100 to 0x17C FWB0 to FWB31 Flash Write Buffer 0 to Flash Write Buffer 32
0xFC0 FLASHPP Flash Peripheral Properties
0xFC8 FLASHCONF Flash Configuration Register
0xFCC ROMSWMAP ROM Third-Party Software
0xFD0 FLASHDMASZ Flash DMA Address Size
0xFD4 FLASHDMAST Flash DMA Starting Address

Table 6-18 GPIO Registers

0x400 GPIODIR GPIO Direction
0x404 GPIOIS GPIO Interrupt Sense
0x408 GPIOIBE GPIO Interrupt Both Edges
0x40C GPIOIEV GPIO Interrupt Event
0x410 GPIOIM GPIO Interrupt Mask
0x414 GPIORIS GPIO Raw Interrupt Status
0x418 GPIOMIS GPIO Masked Interrupt Status
0x41C GPIOICR GPIO Interrupt Clear
0x420 GPIOAFSEL GPIO Alternate Function Select
0x500 GPIODR2R GPIO 2-mA Drive Select
0x504 GPIODR4R GPIO 4-mA Drive Select
0x508 GPIODR8R GPIO 8-mA Drive Select
0x50C GPIOODR GPIO Open Drain Select
0x510 GPIOPUR GPIO Pullup Select
0x514 GPIOPDR GPIO Pulldown Select
0x518 GPIOSLR GPIO Slew Rate Control Select
0x51C GPIODEN GPIO Digital Enable
0x524 GPIOCR GPIO Commit
0x528 GPIOAMSEL GPIO Analog Mode Select
0x52C GPIOPCTL GPIO Port Control
0x538 GPIOSI GPIO Select Interrupt
0x53C GPIODR12R GPIO 12-mA Drive Select
0x540 GPIOWAKEPEN GPIO Wake Pin Enable
0xFC0 GPIOPP GPIO Peripheral Property
0xFC4 GPIOPC GPIO Peripheral Configuration
0xFD0 GPIOPeriphID4 GPIO Peripheral Identification 4
0xFD4 GPIOPeriphID5 GPIO Peripheral Identification 5
0xFD8 GPIOPeriphID6 GPIO Peripheral Identification 6
0xFDC GPIOPeriphID7 GPIO Peripheral Identification 7
0xFE0 GPIOPeriphID0 GPIO Peripheral Identification 0
0xFE4 GPIOPeriphID1 GPIO Peripheral Identification 1
0xFE8 GPIOPeriphID2 GPIO Peripheral Identification 2
0xFEC GPIOPeriphID3 GPIO Peripheral Identification 3
0xFF0 GPIOPCellID0 GPIO PrimeCell Identification 0
0xFF4 GPIOPCellID1 GPIO PrimeCell Identification 1
0xFF8 GPIOPCellID2 GPIO PrimeCell Identification 2
0xFFC GPIOPCellID3 GPIO PrimeCell Identification 3

Table 6-19 GPTM Registers

0x0 GPTMCFG GPTM Configuration
0x4 GPTMTAMR GPTM Timer A Mode
0x8 GPTMTBMR GPTM Timer B Mode
0x10 GPTMSYNC GPTM Synchronize
0x18 GPTMIMR GPTM Interrupt Mask
0x1C GPTMRIS GPTM Raw Interrupt Status
0x20 GPTMMIS GPTM Masked Interrupt Status
0x24 GPTMICR GPTM Interrupt Clear
0x28 GPTMTAILR GPTM Timer A Interval Load
0x2C GPTMTBILR GPTM Timer B Interval Load
0x38 GPTMTAPR GPTM Timer A Prescale
0x3C GPTMTBPR GPTM Timer B Prescale
0x40 GPTMTAPMR GPTM TimerA Prescale Match
0x44 GPTMTBPMR GPTM TimerB Prescale Match
0x50 GPTMTAV GPTM Timer A Value
0x54 GPTMTBV GPTM Timer B Value
0x5C GPTMTAPS GPTM Timer A Prescale Snapshot
0x60 GPTMTBPS GPTM Timer B Prescale Snapshot
0xFC0 GPTMPP GPTM Peripheral Properties
0xFC8 GPTMCC GPTM Clock Configuration

Table 6-20 HIB Registers

0x0 HIBRTCC Hibernation RTC Counter
0x4 HIBRTCM0 Hibernation RTC Match 0
0xC HIBRTCLD Hibernation RTC Load
0x10 HIBCTL Hibernation Control
0x14 HIBIM Hibernation Interrupt Mask
0x18 HIBRIS Hibernation Raw Interrupt Status
0x1C HIBMIS Hibernation Masked Interrupt Status
0x20 HIBIC Hibernation Interrupt Clear
0x24 HIBRTCT Hibernation RTC Trim
0x28 HIBRTCSS Hibernation RTC Sub Seconds
0x2C HIBIO Hibernation IO Configuration
0x30 to 0x6F HIBDATA Hibernation Data
0x300 HIBCALCTL Hibernation Calendar Control
0x310 HIBCAL0 Hibernation Calendar 0
0x314 HIBCAL1 Hibernation Calendar 1
0x320 HIBCALLD0 Hibernation Calendar Load 0
0x324 HIBCALLD1 Hibernation Calendar Load 1
0x330 HIBCALM0 Hibernation Calendar Match 0
0x334 HIBCALM1 Hibernation Calendar Match 1
0x360 HIBLOCK Hibernation Lock
0x400 HIBTPCTL HIB Tamper Control
0x404 HIBTPSTAT HIB Tamper Status
0x410 HIBTPIO HIB Tamper I/O Control
0x4E0 HIBTPLOG0 HIB Tamper Log 0
0x4E4 HIBTPLOG1 HIB Tamper Log 1
0x4E8 HIBTPLOG2 HIB Tamper Log 2
0x4EC HIBTPLOG3 HIB Tamper Log 3
0x4F0 HIBTPLOG4 HIB Tamper Log 4
0x4F4 HIBTPLOG5 HIB Tamper Log 5
0x4F8 HIBTPLOG6 HIB Tamper Log 6
0x4FC HIBTPLOG7 HIB Tamper Log 7
0xFC0 HIBPP Hibernation Peripheral Properties
0xFC8 HIBCC Hibernation Clock Control

Table 6-21 I2C Registers

0x0 I2CMSA I2C Master Slave Address
0x4 I2CMCS I2C Master Control/Status
0x8 I2CMDR I2C Master Data
0xC I2CMTPR I2C Master Timer Period
0x10 I2CMIMR I2C Master Interrupt Mask
0x14 I2CMRIS I2C Master Raw Interrupt Status
0x18 I2CMMIS I2C Master Masked Interrupt Status
0x1C I2CMICR I2C Master Interrupt Clear
0x20 I2CMCR I2C Master Configuration
0x24 I2CMCLKOCNT I2C Master Clock Low Time-out Count
0x2C I2CMBMON I2C Master Bus Monitor
0x30 I2CMBLEN I2C Master Burst Length
0x34 I2CMBCNT I2C Master Burst Count
0x800 I2CSOAR I2C Slave Own Address
0x804 I2CSCSR I2C Slave Control/Status
0x808 I2CSDR I2C Slave Data
0x80C I2CSIMR I2C Slave Interrupt Mask
0x810 I2CSRIS I2C Slave Raw Interrupt Status
0x814 I2CSMIS I2C Slave Masked Interrupt Status
0x818 I2CSICR I2C Slave Interrupt Clear
0x81C I2CSOAR2 I2C Slave Own Address 2
0x820 I2CSACKCTL I2C Slave ACK Control
0xFC0 I2CPP I2C Peripheral Properties
0xFC4 I2CPC I2C Peripheral Configuration

Table 6-22 LCD Registers

0x0 LCDPID LCD PID Register Format
0x4 LCDCTL LCD Control
0x10 LIDDCS0CFG LCD LIDD CS0 Configuration
0x14 LIDDCS0ADDR LIDD CS0 Read/Write Address
0x18 LIDDCS0DATA LIDD CS0 Data Read/Write Initiation
0x1C LIDDCS1CFG LIDD CS1 Configuration
0x20 LIDDCS1ADDR LIDD CS1 Address Read/Write Initiation
0x24 LIDDCS1DATA LIDD CS1 Data Read/Write Initiation
0x28 LCDRASTRCTL LCD Raster Control
0x2C LCDRASTRTIM0 LCD Raster Timing 0
0x30 LCDRASTRTIM1 LCD Raster Timing 1
0x34 LCDRASTRTIM2 LCD Raster Timing 2
0x38 LCDRASTRSUBP1 LCD Raster Subpanel Display 1
0x3C LCDRASTRSUBP2 LCD Raster Subpanel Display 2
0x44 LCDDMABAFB0 LCD DMA Frame Buffer 0 Base Address
0x48 LCDDMACAFB0 LCD DMA Frame Buffer 0 Ceiling Address
0x4C LCDDMABAFB1 LCD DMA Frame Buffer 1 Base Address
0x50 LCDDMACAFB1 LCD DMA Frame Buffer 1 Ceiling Address
0x54 LCDSYSCFG LCD System Configuration Register
0x58 LCDRISSET LCD Interrupt Raw Status and Set Register
0x5C LCDMISCLR LCD Interrupt Status and Clear
0x60 LCDIM LCD Interrupt Mask
0x64 LCDIENC LCD Interrupt Enable Clear
0x6C LCDCLKEN LCD Clock Enable
0x70 LCDCLKRESET LCD Clock Resets

Table 6-23 µDMA Registers

0x0 DMASTAT DMA Status
0x4 DMACFG DMA Configuration
0x8 DMACTLBASE DMA Channel Control Base Pointer
0xC DMAALTBASE DMA Alternate Channel Control Base Pointer
0x10 DMAWAITSTAT DMA Channel Wait-on-Request Status
0x14 DMASWREQ DMA Channel Software Request
0x18 DMAUSEBURSTSET DMA Channel Useburst Set
0x1C DMAUSEBURSTCLR DMA Channel Useburst Clear
0x20 DMAREQMASKSET DMA Channel Request Mask Set
0x24 DMAREQMASKCLR DMA Channel Request Mask Clear
0x28 DMAENASET DMA Channel Enable Set
0x2C DMAENACLR DMA Channel Enable Clear
0x30 DMAALTSET DMA Channel Primary Alternate Set
0x34 DMAALTCLR DMA Channel Primary Alternate Clear
0x38 DMAPRIOSET DMA Channel Priority Set
0x3C DMAPRIOCLR DMA Channel Priority Clear
0x4C DMAERRCLR DMA Bus Error Clear
0x510 DMACHMAP0 DMA Channel Map Select 0
0x514 DMACHMAP1 DMA Channel Map Select 1
0x518 DMACHMAP2 DMA Channel Map Select 2
0x51C DMACHMAP3 DMA Channel Map Select 3
0xFD0 DMAPeriphID4 DMA Peripheral Identification 4
0xFE0 DMAPeriphID0 DMA Peripheral Identification 0
0xFE4 DMAPeriphID1 DMA Peripheral Identification 1
0xFE8 DMAPeriphID2 DMA Peripheral Identification 2
0xFEC DMAPeriphID3 DMA Peripheral Identification 3
0xFF0 DMAPCellID0 DMA PrimeCell Identification 0
0xFF4 DMAPCellID1 DMA PrimeCell Identification 1
0xFF8 DMAPCellID2 DMA PrimeCell Identification 2
0xFFC DMAPCellID3 DMA PrimeCell Identification 3

Table 6-24 µDMA Channel Control Structure Registers

0x0 DMASRCENDP DMA Channel Source Address End Pointer
0x4 DMADSTENDP DMA Channel Destination Address End Pointer
0x8 DMACHCTL DMA Channel Control Word

Table 6-25 PWM Registers

0x0 PWMCTL PWM Master Control
0x4 PWMSYNC PWM Time Base Sync
0x8 PWMENABLE PWM Output Enable
0xC PWMINVERT PWM Output Inversion
0x10 PWMFAULT PWM Output Fault
0x14 PWMINTEN PWM Interrupt Enable
0x18 PWMRIS PWM Raw Interrupt Status
0x1C PWMISC PWM Interrupt Status and Clear
0x24 PWMFAULTVAL PWM Fault Condition Value
0x28 PWMENUPD PWM Enable Update
0x40 PWM0CTL PWM0 Control
0x44 PWM0INTEN PWM0 Interrupt and Trigger Enable
0x48 PWM0RIS PWM0 Raw Interrupt Status
0x4C PWM0ISC PWM0 Interrupt Status and Clear
0x50 PWM0LOAD PWM0 Load
0x54 PWM0COUNT PWM0 Counter
0x58 PWM0CMPA PWM0 Compare A
0x5C PWM0CMPB PWM0 Compare B
0x60 PWM0GENA PWM0 Generator A Control
0x64 PWM0GENB PWM0 Generator B Control
0x68 PWM0DBCTL PWM0 Dead-Band Control
0x6C PWM0DBRISE PWM0 Dead-Band Rising-Edge Delay
0x70 PWM0DBFALL PWM0 Dead-Band Falling-Edge-Delay
0x74 PWM0FLTSRC0 PWM0 Fault Source 0
0x78 PWM0FLTSRC1 PWM0 Fault Source 1
0x7C PWM0MINFLTPER PWM0 Minimum Fault Period
0x080 PWM1CTL PWM1 Control
0x084 PWM1INTEN PWM1 Interrupt and Trigger Enable
0x088 PWM1RIS PWM1 Raw Interrupt Status
0x08C PWM1ISC PWM1 Interrupt Status and Clear
0x090 PWM1LOAD PWM1 Load
0x094 PWM1COUNT PWM1 Counter
0x098 PWM1CMPA PWM1 Compare A
0x09C PWM1CMPB PWM1 Compare B
0x0A0 PWM1GENA PWM1 Generator A Control
0x0A4 PWM1GENB PWM1 Generator B Control
0x0A8 PWM1DBCTL PWM1 Dead-Band Control
0x0AC PWM1DBRISE PWM1 Dead-Band Rising-Edge Delay
0x0B0 PWM1DBFALL PWM1 Dead-Band Falling-Edge-Delay
0x0B4 PWM1FLTSRC0 PWM1 Fault Source 0
0x0B8 PWM1FLTSRC1 PWM1 Fault Source 1
0x0BC PWM1MINFLTPER PWM1 Minimum Fault Period
0x0C0 PWM2CTL PWM2 Control
0x0C4 PWM2INTEN PWM2 Interrupt and Trigger Enable
0x0C8 PWM2RIS PWM2 Raw Interrupt Status
0x0CC PWM2ISC PWM2 Interrupt Status and Clear
0x0D0 PWM2LOAD PWM2 Load
0x0D4 PWM2COUNT PWM2 Counter
0x0D8 PWM2CMPA PWM2 Compare A
0x0DC PWM2CMPB PWM2 Compare B
0x0E0 PWM2GENA PWM2 Generator A Control
0x0E4 PWM2GENB PWM2 Generator B Control
0x0E8 PWM2DBCTL PWM2 Dead-Band Control
0x0EC PWM2DBRISE PWM2 Dead-Band Rising-Edge Delay
0x0F0 PWM2DBFALL PWM2 Dead-Band Falling-Edge-Delay
0x0F4 PWM2FLTSRC0 PWM2 Fault Source 0
0x0F8 PWM2FLTSRC1 PWM2 Fault Source 1
0x0FC PWM2MINFLTPER PWM2 Minimum Fault Period
0x100 PWM3CTL PWM3 Control
0x104 PWM3INTEN PWM3 Interrupt and Trigger Enable
0x108 PWM3RIS PWM3 Raw Interrupt Status
0x10C PWM3ISC PWM3 Interrupt Status and Clear
0x110 PWM3LOAD PWM3 Load
0x114 PWM3COUNT PWM3 Counter
0x118 PWM3CMPA PWM3 Compare A
0x11C PWM3CMPB PWM3 Compare B
0x120 PWM3GENA PWM3 Generator A Control
0x124 PWM3GENB PWM3 Generator B Control
0x128 PWM3DBCTL PWM3 Dead-Band Control
0x12C PWM3DBRISE PWM3 Dead-Band Rising-Edge Delay
0x130 PWM3DBFALL PWM3 Dead-Band Falling-Edge-Delay
0x134 PWM3FLTSRC0 PWM3 Fault Source 0
0x138 PWM3FLTSRC1 PWM3 Fault Source 1
0x13C PWM3MINFLTPER PWM3 Minimum Fault Period
0x800 PWM0FLTSEN PWM0 Fault Pin Logic Sense
0x804 PWM0FLTSTAT0 PWM0 Fault Status 0
0x808 PWM0FLTSTAT1 PWM0 Fault Status 1
0x880 PWM1FLTSEN PWM1 Fault Pin Logic Sense
0x884 PWM1FLTSTAT0 PWM1 Fault Status 0
0x888 PWM1FLTSTAT1 PWM1 Fault Status 1
0x900 PWM2FLTSEN PWM2 Fault Pin Logic Sense
0x904 PWM2FLTSTAT0 PWM2 Fault Status 0
0x908 PWM2FLTSTAT1 PWM2 Fault Status 1
0x980 PWM3FLTSEN PWM3 Fault Pin Logic Sense
0x984 PWM3FLTSTAT0 PWM3 Fault Status 0
0x988 PWM3FLTSTAT1 PWM3 Fault Status 1
0xFC0 PWMPP PWM Peripheral Properties
0xFC8 PWMCC PWM Clock Configuration

Table 6-26 QEI Registers

0x0 QEICTL QEI Control
0x4 QEISTAT QEI Status
0x8 QEIPOS QEI Position
0xC QEIMAXPOS QEI Maximum Position
0x10 QEILOAD QEI Timer Load
0x14 QEITIME QEI Timer
0x18 QEICOUNT QEI Velocity Counter
0x1C QEISPEED QEI Velocity
0x20 QEIINTEN QEI Interrupt Enable
0x24 QEIRIS QEI Raw Interrupt Status
0x28 QEIISC QEI Interrupt Status and Clear

Table 6-27 QSSI Registers

0x0 SSICR0 QSSI Control 0
0x4 SSICR1 QSSI Control 1
0x10 SSICPSR QSSI Clock Prescale
0x14 SSIIM QSSI Interrupt Mask
0x18 SSIRIS QSSI Raw Interrupt Status
0x1C SSIMIS QSSI Masked Interrupt Status
0x20 SSIICR QSSI Interrupt Clear
0xFC0 SSIPP QSSI Peripheral Properties
0xFC8 SSICC QSSI Clock Configuration
0xFD0 SSIPeriphID4 QSSI Peripheral Identification 4
0xFD4 SSIPeriphID5 QSSI Peripheral Identification 5
0xFD8 SSIPeriphID6 QSSI Peripheral Identification 6
0xFDC SSIPeriphID7 QSSI Peripheral Identification 7
0xFE0 SSIPeriphID0 QSSI Peripheral Identification 0
0xFE4 SSIPeriphID1 QSSI Peripheral Identification 1
0xFE8 SSIPeriphID2 QSSI Peripheral Identification 2
0xFEC SSIPeriphID3 QSSI Peripheral Identification 3
0xFF0 SSIPCellID0 QSSI PrimeCell Identification 0
0xFF4 SSIPCellID1 QSSI PrimeCell Identification 1
0xFF8 SSIPCellID2 QSSI PrimeCell Identification 2
0xFFC SSIPCellID3 QSSI PrimeCell Identification 3

Table 6-28 SHA/MD5 Registers

0x000 SHA_ODIGEST_A SHA Outer Digest A
0x004 SHA_ODIGEST_B SHA Outer Digest B
0x008 SHA_ODIGEST_C SHA Outer Digest C
0x00C SHA_ODIGEST_D SHA Outer Digest D
0x010 SHA_ODIGEST_E SHA Outer Digest E
0x014 SHA_ODIGEST_F SHA Outer Digest F
0x018 SHA_ODIGEST_G SHA Outer Digest G
0x01C SHA_ODIGEST_H SHA Outer Digest H
0x020 SHA_IDIGEST_A SHA Inner Digest A
0x024 SHA_IDIGEST_B SHA Inner Digest B
0x028 SHA_IDIGEST_C SHA Inner Digest C
0x02C SHA_IDIGEST_D SHA Inner Digest D
0x030 SHA_IDIGEST_E SHA Inner Digest E
0x034 SHA_IDIGEST_F SHA Inner Digest F
0x038 SHA_IDIGEST_G SHA Inner Digest G
0x03C SHA_IDIGEST_H SHA Inner Digest H
0x40 SHA_DIGEST_COUNT SHA Digest Count
0x44 SHA_MODE SHA Mode
0x48 SHA_LENGTH SHA Length
0x080 SHA_DATA_0_IN SHA Data 0 Input
0x084 SHA_DATA_1_IN SHA Data 1 Input
0x088 SHA_DATA_2_IN SHA Data 2 Input
0x08C SHA_DATA_3_IN SHA Data 3 Input
0x090 SHA_DATA_4_IN SHA Data 4 Input
0x094 SHA_DATA_5_IN SHA Data 5 Input
0x098 SHA_DATA_6_IN SHA Data 6 Input
0x09C SHA_DATA_7_IN SHA Data 7 Input
0x0A0 SHA_DATA_8_IN SHA Data 8 Input
0x0A4 SHA_DATA_9_IN SHA Data 9 Input
0x0A8 SHA_DATA_10_IN SHA Data 10 Input
0x0AC SHA_DATA_11_IN SHA Data 11 Input
0x0B0 SHA_DATA_12_IN SHA Data 12 Input
0x0B4 SHA_DATA_13_IN SHA Data 13 Input
0x0B8 SHA_DATA_14_IN SHA Data 14 Input
0x0BC SHA_DATA_15_IN SHA Data 15 Input
0x100 SHA_REVISION SHA Revision
0x110 SHA_SYSCONFIG SHA System Configuration
0x114 SHA_SYSSTATUS SHA System Status
0x118 SHA_IRQSTATUS SHA Interrupt Status
0x11C SHA_IRQENABLE SHA Interrupt Enable

Table 6-29 SHA/MD5 µDMA Registers

0x10 SHA_DMAIM SHA DMA Interrupt Mask
0x14 SHA_DMARIS SHA DMA Raw Interrupt Status
0x18 SHA_DMAMIS SHA DMA Masked Interrupt Status
0x1C SHA_DMAIC SHA DMA Interrupt Clear

Table 6-30 System Control Memory Registers

0xD4 RVP Reset Vector Pointer
0x1D0 BOOTCFG Boot Configuration
0x1E0 to 0x1EC USER_REG_0 to USER_REG_3 User Register 0 to User Register 3
0x200 to 0x23C FMPRE_0 to FMPRE_15 Flash Memory Protection Read Enable 0 to Flash Memory Protection Read Enable 15
0x400 to 0x43C FMPPE_0 to FMPPE_15 Flash Memory Protection Program Enable 0 to Flash Memory Protection Program Enable 15

Table 6-31 System Exception Registers

0x0 SYSEXCRIS System Exception Raw Interrupt Status
0x4 SYSEXCIM System Exception Interrupt Mask
0x8 SYSEXCMIS System Exception Masked Interrupt Status
0xC SYSEXCIC System Exception Interrupt Clear

Table 6-32 UART Registers

0x4 UARTRSR/UARTECR UART Receive Status/Error Clear
0x20 UARTILPR UART IrDA Low-Power Register
0x24 UARTIBRD UART Integer Baud-Rate Divisor
0x28 UARTFBRD UART Fractional Baud-Rate Divisor
0x2C UARTLCRH UART Line Control
0x30 UARTCTL UART Control
0x34 UARTIFLS UART Interrupt FIFO Level Select
0x38 UARTIM UART Interrupt Mask
0x3C UARTRIS UART Raw Interrupt Status
0x40 UARTMIS UART Masked Interrupt Status
0x44 UARTICR UART Interrupt Clear
0xA4 UART9BITADDR UART 9-Bit Self Address
0xA8 UART9BITAMASK UART 9-Bit Self Address Mask
0xFC0 UARTPP UART Peripheral Properties
0xFC8 UARTCC UART Clock Configuration
0xFD0 UARTPeriphID4 UART Peripheral Identification 4
0xFD4 UARTPeriphID5 UART Peripheral Identification 5
0xFD8 UARTPeriphID6 UART Peripheral Identification 6
0xFDC UARTPeriphID7 UART Peripheral Identification 7
0xFE0 UARTPeriphID0 UART Peripheral Identification 0
0xFE4 UARTPeriphID1 UART Peripheral Identification 1
0xFE8 UARTPeriphID2 UART Peripheral Identification 2
0xFEC UARTPeriphID3 UART Peripheral Identification 3
0xFF0 UARTPCellID0 UART PrimeCell Identification 0
0xFF4 UARTPCellID1 UART PrimeCell Identification 1
0xFF8 UARTPCellID2 UART PrimeCell Identification 2
0xFFC UARTPCellID3 UART PrimeCell Identification 3

Table 6-33 USB Registers

0x0 USBFADDR USB Device Functional Address
0x2 USBTXIS USB Transmit Interrupt Status
0x4 USBRXIS USB Receive Interrupt Status
0x6 USBTXIE USB Transmit Interrupt Enable
0x8 USBRXIE USB Receive Interrupt Enable
0xA USBIS USB General Interrupt Status
0xB USBIE USB Interrupt Enable
0xC USBFRAME USB Frame Value
0xE USBEPIDX USB Endpoint Index
0x20 USBFIFO0 USB FIFO Endpoint 0
0x24 USBFIFO1 USB FIFO Endpoint 1
0x28 USBFIFO2 USB FIFO Endpoint 2
0x2C USBFIFO3 USB FIFO Endpoint 3
0x30 USBFIFO4 USB FIFO Endpoint 4
0x34 USBFIFO5 USB FIFO Endpoint 5
0x38 USBFIFO6 USB FIFO Endpoint 6
0x3C USBFIFO7 USB FIFO Endpoint 7
0x60 USBDEVCTL USB Device Control
0x61 USBCCONF USB Common Configuration
0x62 USBTXFIFOSZ USB Transmit Dynamic FIFO Sizing
0x63 USBRXFIFOSZ USB Receive Dynamic FIFO Sizing
0x64 USBTXFIFOADD USB Transmit FIFO Start Address
0x66 USBRXFIFOADD USB Receive FIFO Start Address
0x75 ULPIREGADDR USB ULPI Register Address
0x76 ULPIREGCTL USB ULPI Register Control
0x78 USBEPINFO USB Endpoint Information
0x79 USBRAMINFO USB RAM Information
0x7A USBCONTIM USB Connect Timing
0x7C USBHSEOF USB High-Speed Last Transaction to End of Frame Timing
0x7D USBFSEOF USB Full-Speed Last Transaction to End of Frame Timing
0x7E USBLSEOF USB Low-Speed Last Transaction to End of Frame Timing
0x80 USBTXFUNCADDR0 USB Transmit Functional Address Endpoint 0
0x82 USBTXHUBADDR0 USB Transmit Hub Address Endpoint 0
0x83 USBTXHUBPORT0 USB Transmit Hub Port Endpoint 0
0x88 USBTXFUNCADDR1 USB Transmit Functional Address Endpoint 1
0x8A USBTXHUBADDR1 USB Transmit Hub Address Endpoint 1
0x8B USBTXHUBPORT1 USB Transmit Hub Port Endpoint 1
0x8C USBRXFUNCADDR1 USB Receive Functional Address Endpoint 1
0x8E USBRXHUBADDR1 USB Receive Hub Address Endpoint 1
0x8F USBRXHUBPORT1 USB Receive Hub Port Endpoint 1
0x90 USBTXFUNCADDR2 USB Transmit Functional Address Endpoint 2
0x92 USBTXHUBADDR2 USB Transmit Hub Address Endpoint 2
0x93 USBTXHUBPORT2 USB Transmit Hub Port Endpoint 2
0x94 USBRXFUNCADDR2 USB Receive Functional Address Endpoint 2
0x96 USBRXHUBADDR2 USB Receive Hub Address Endpoint 2
0x97 USBRXHUBPORT2 USB Receive Hub Port Endpoint 2
0x98 USBTXFUNCADDR3 USB Transmit Functional Address Endpoint 3
0x9A USBTXHUBADDR3 USB Transmit Hub Address Endpoint 3
0x9B USBTXHUBPORT3 USB Transmit Hub Port Endpoint 3
0x9C USBRXFUNCADDR3 USB Receive Functional Address Endpoint 3
0x9E USBRXHUBADDR3 USB Receive Hub Address Endpoint 3
0x9F USBRXHUBPORT3 USB Receive Hub Port Endpoint 3
0xA0 USBTXFUNCADDR4 USB Transmit Functional Address Endpoint 4
0xA2 USBTXHUBADDR4 USB Transmit Hub Address Endpoint 4
0xA3 USBTXHUBPORT4 USB Transmit Hub Port Endpoint 4
0xA4 USBRXFUNCADDR4 USB Receive Functional Address Endpoint 4
0xA6 USBRXHUBADDR4 USB Receive Hub Address Endpoint 4
0xA7 USBRXHUBPORT4 USB Receive Hub Port Endpoint 4
0xA8 USBTXFUNCADDR5 USB Transmit Functional Address Endpoint 5
0xAA USBTXHUBADDR5 USB Transmit Hub Address Endpoint 5
0xAB USBTXHUBPORT5 USB Transmit Hub Port Endpoint 5
0xAC USBRXFUNCADDR5 USB Receive Functional Address Endpoint 5
0xAE USBRXHUBADDR5 USB Receive Hub Address Endpoint 5
0xAF USBRXHUBPORT5 USB Receive Hub Port Endpoint 5
0xB0 USBTXFUNCADDR6 USB Transmit Functional Address Endpoint 6
0xB2 USBTXHUBADDR6 USB Transmit Hub Address Endpoint 6
0xB3 USBTXHUBPORT6 USB Transmit Hub Port Endpoint 6
0xB4 USBRXFUNCADDR6 USB Receive Functional Address Endpoint 6
0xB6 USBRXHUBADDR6 USB Receive Hub Address Endpoint 6
0xB7 USBRXHUBPORT6 USB Receive Hub Port Endpoint 6
0xB8 USBTXFUNCADDR7 USB Transmit Functional Address Endpoint 7
0xBA USBTXHUBADDR7 USB Transmit Hub Address Endpoint 7
0xBB USBTXHUBPORT7 USB Transmit Hub Port Endpoint 7
0xBC USBRXFUNCADDR7 USB Receive Functional Address Endpoint 7
0xBE USBRXHUBADDR7 USB Receive Hub Address Endpoint 7
0xBF USBRXHUBPORT7 USB Receive Hub Port Endpoint 7
0x102 USBCSRL0 USB Control and Status Endpoint 0 Low
0x103 USBCSRH0 USB Control and Status Endpoint 0 High
0x108 USBCOUNT0 USB Receive Byte Count Endpoint 0
0x10A USBTYPE0 USB Type Endpoint 0
0x110 USBTXMAXP1 USB Maximum Transmit Data Endpoint 1
0x112 USBTXCSRL1 USB Transmit Control and Status Endpoint 1 Low
0x113 USBTXCSRH1 USB Transmit Control and Status Endpoint 1 High
0x114 USBRXMAXP1 USB Maximum Receive Data Endpoint 1
0x116 USBRXCSRL1 USB Receive Control and Status Endpoint 1 Low
0x117 USBRXCSRH1 USB Receive Control and Status Endpoint 1 High
0x118 USBRXCOUNT1 USB Receive Byte Count Endpoint 1
0x11A USBTXTYPE1 USB Host Transmit Configure Type Endpoint 1
0x11B USBTXINTERVAL1 USB Host Transmit Interval Endpoint 1
0x11C USBRXTYPE1 USB Host Configure Receive Type Endpoint 1
0x11D USBRXINTERVAL1 USB Host Receive Polling Interval Endpoint 1
0x120 USBTXMAXP2 USB Maximum Transmit Data Endpoint 2
0x122 USBTXCSRL2 USB Transmit Control and Status Endpoint 2 Low
0x123 USBTXCSRH2 USB Transmit Control and Status Endpoint 2 High
0x124 USBRXMAXP2 USB Maximum Receive Data Endpoint 2
0x126 USBRXCSRL2 USB Receive Control and Status Endpoint 2 Low
0x127 USBRXCSRH2 USB Receive Control and Status Endpoint 2 High
0x128 USBRXCOUNT2 USB Receive Byte Count Endpoint 2
0x12A USBTXTYPE2 USB Host Transmit Configure Type Endpoint 2
0x12B USBTXINTERVAL2 USB Host Transmit Interval Endpoint 2
0x12C USBRXTYPE2 USB Host Configure Receive Type Endpoint 2
0x12D USBRXINTERVAL2 USB Host Receive Polling Interval Endpoint 2
0x130 USBTXMAXP3 USB Maximum Transmit Data Endpoint 3
0x132 USBTXCSRL3 USB Transmit Control and Status Endpoint 3 Low
0x133 USBTXCSRH3 USB Transmit Control and Status Endpoint 3 High
0x134 USBRXMAXP3 USB Maximum Receive Data Endpoint 3
0x136 USBRXCSRL3 USB Receive Control and Status Endpoint 3 Low
0x137 USBRXCSRH3 USB Receive Control and Status Endpoint 3 High
0x138 USBRXCOUNT3 USB Receive Byte Count Endpoint 3
0x13A USBTXTYPE3 USB Host Transmit Configure Type Endpoint 3
0x13B USBTXINTERVAL3 USB Host Transmit Interval Endpoint 3
0x13C USBRXTYPE3 USB Host Configure Receive Type Endpoint 3
0x13D USBRXINTERVAL3 USB Host Receive Polling Interval Endpoint 3
0x140 USBTXMAXP4 USB Maximum Transmit Data Endpoint 4
0x142 USBTXCSRL4 USB Transmit Control and Status Endpoint 4 Low
0x143 USBTXCSRH4 USB Transmit Control and Status Endpoint 4 High
0x144 USBRXMAXP4 USB Maximum Receive Data Endpoint 4
0x146 USBRXCSRL4 USB Receive Control and Status Endpoint 4 Low
0x147 USBRXCSRH4 USB Receive Control and Status Endpoint 4 High
0x148 USBRXCOUNT4 USB Receive Byte Count Endpoint 4
0x14A USBTXTYPE4 USB Host Transmit Configure Type Endpoint 4
0x14B USBTXINTERVAL4 USB Host Transmit Interval Endpoint 4
0x14C USBRXTYPE4 USB Host Configure Receive Type Endpoint 4
0x14D USBRXINTERVAL4 USB Host Receive Polling Interval Endpoint 4
0x150 USBTXMAXP5 USB Maximum Transmit Data Endpoint 5
0x152 USBTXCSRL5 USB Transmit Control and Status Endpoint 5 Low
0x153 USBTXCSRH5 USB Transmit Control and Status Endpoint 5 High
0x154 USBRXMAXP5 USB Maximum Receive Data Endpoint 5
0x156 USBRXCSRL5 USB Receive Control and Status Endpoint 5 Low
0x157 USBRXCSRH5 USB Receive Control and Status Endpoint 5 High
0x158 USBRXCOUNT5 USB Receive Byte Count Endpoint 5
0x15A USBTXTYPE5 USB Host Transmit Configure Type Endpoint 5
0x15B USBTXINTERVAL5 USB Host Transmit Interval Endpoint 5
0x15C USBRXTYPE5 USB Host Configure Receive Type Endpoint 5
0x15D USBRXINTERVAL5 USB Host Receive Polling Interval Endpoint 5
0x160 USBTXMAXP6 USB Maximum Transmit Data Endpoint 6
0x162 USBTXCSRL6 USB Transmit Control and Status Endpoint 6 Low
0x163 USBTXCSRH6 USB Transmit Control and Status Endpoint 6 High
0x164 USBRXMAXP6 USB Maximum Receive Data Endpoint 6
0x166 USBRXCSRL6 USB Receive Control and Status Endpoint 6 Low
0x167 USBRXCSRH6 USB Receive Control and Status Endpoint 6 High
0x168 USBRXCOUNT6 USB Receive Byte Count Endpoint 6
0x16A USBTXTYPE6 USB Host Transmit Configure Type Endpoint 6
0x16B USBTXINTERVAL6 USB Host Transmit Interval Endpoint 6
0x16C USBRXTYPE6 USB Host Configure Receive Type Endpoint 6
0x16D USBRXINTERVAL6 USB Host Receive Polling Interval Endpoint 6
0x170 USBTXMAXP7 USB Maximum Transmit Data Endpoint 7
0x172 USBTXCSRL7 USB Transmit Control and Status Endpoint 7 Low
0x173 USBTXCSRH7 USB Transmit Control and Status Endpoint 7 High
0x174 USBRXMAXP7 USB Maximum Receive Data Endpoint 7
0x176 USBRXCSRL7 USB Receive Control and Status Endpoint 7 Low
0x177 USBRXCSRH7 USB Receive Control and Status Endpoint 7 High
0x178 USBRXCOUNT7 USB Receive Byte Count Endpoint 7
0x17A USBTXTYPE7 USB Host Transmit Configure Type Endpoint 7
0x17B USBTXINTERVAL7 USB Host Transmit Interval Endpoint 7
0x17C USBRXTYPE7 USB Host Configure Receive Type Endpoint 7
0x17D USBRXINTERVAL7 USB Host Receive Polling Interval Endpoint 7
0x200 USBDMAINTR USB DMA Interrupt
0x204 USBDMACTL0 USB DMA Control 0
0x208 USBDMAADDR0 USB DMA Address 0
0x214 USBDMACTL1 USB DMA Control 1
0x218 USBDMAADDR1 USB DMA Address 1
0x224 USBDMACTL2 USB DMA Control 2
0x228 USBDMAADDR2 USB DMA Address 2
0x234 USBDMACTL3 USB DMA Control 3
0x238 USBDMAADDR3 USB DMA Address 3
0x244 USBDMACTL4 USB DMA Control 4
0x248 USBDMAADDR4 USB DMA Address 4
0x254 USBDMACTL5 USB DMA Control 5
0x258 USBDMAADDR5 USB DMA Address 5
0x264 USBDMACTL6 USB DMA Control 6
0x268 USBDMAADDR6 USB DMA Address 6
0x274 USBDMACTL7 USB DMA Control 7
0x278 USBDMAADDR7 USB DMA Address 7
0x304 USBRQPKTCOUNT1 USB Request Packet Count in Block Transfer Endpoint 1
0x308 USBRQPKTCOUNT2 USB Request Packet Count in Block Transfer Endpoint 2
0x30C USBRQPKTCOUNT3 USB Request Packet Count in Block Transfer Endpoint 3
0x310 USBRQPKTCOUNT4 USB Request Packet Count in Block Transfer Endpoint 4
0x314 USBRQPKTCOUNT5 USB Request Packet Count in Block Transfer Endpoint 5
0x318 USBRQPKTCOUNT6 USB Request Packet Count in Block Transfer Endpoint 6
0x31C USBRQPKTCOUNT7 USB Request Packet Count in Block Transfer Endpoint 7
0x340 USBRXDPKTBUFDIS USB Receive Double Packet Buffer Disable
0x342 USBTXDPKTBUFDIS USB Transmit Double Packet Buffer Disable
0x344 USBCTO USB Chirp Time-out
0x346 USBHHSRTN USB High Speed to UTM Operating Delay
0x348 USBHSBT USB High Speed Time-out Adder
0x360 USBLPMATTR USB LPM Attributes
0x363 USBLPMIM USB LPM Interrupt Mask
0x364 USBLPMRIS USB LPM Raw Interrupt Status
0x365 USBLPMFADDR USB LPM Function Address
0x400 USBEPC USB External Power Control
0x404 USBEPCRIS USB External Power Control Raw Interrupt Status
0x408 USBEPCIM USB External Power Control Interrupt Mask
0x40C USBEPCISC USB External Power Control Interrupt Status and Clear
0x410 USBDRRIS USB Device RESUME Raw Interrupt Status
0x414 USBDRIM USB Device RESUME Interrupt Mask
0x418 USBDRISC USB Device RESUME Interrupt Status and Clear
0x41C USBGPCS USB General-Purpose Control and Status
0x430 USBVDC USB VBUS Droop Control
0x434 USBVDCRIS USB VBUS Droop Control Raw Interrupt Status
0x438 USBVDCIM USB VBUS Droop Control Interrupt Mask
0x43C USBVDCISC USB VBUS Droop Control Interrupt Status and Clear
0xFC0 USBPP USB Peripheral Properties
0xFC4 USBPC USB Peripheral Configuration
0xFC8 USBCC USB Clock Configuration

Table 6-34 WDT Registers

0x0 WDTLOAD Watchdog Load
0x4 WDTVALUE Watchdog Value
0x8 WDTCTL Watchdog Control
0xC WDTICR Watchdog Interrupt Clear
0x10 WDTRIS Watchdog Raw Interrupt Status
0x14 WDTMIS Watchdog Masked Interrupt Status
0x418 WDTTEST Watchdog Test
0xC00 WDTLOCK Watchdog Lock
0xFD0 WDTPeriphID4 Watchdog Peripheral Identification 4
0xFD4 WDTPeriphID5 Watchdog Peripheral Identification 5
0xFD8 WDTPeriphID6 Watchdog Peripheral Identification 6
0xFDC WDTPeriphID7 Watchdog Peripheral Identification 7
0xFE0 WDTPeriphID0 Watchdog Peripheral Identification 0
0xFE4 WDTPeriphID1 Watchdog Peripheral Identification 1
0xFE8 WDTPeriphID2 Watchdog Peripheral Identification 2
0xFEC WDTPeriphID3 Watchdog Peripheral Identification 3
0xFF0 WDTPCellID0 Watchdog PrimeCell Identification 0
0xFF4 WDTPCellID1 Watchdog PrimeCell Identification 1
0xFF8 WDTPCellID2 Watchdog PrimeCell Identification 2
0xFFC WDTPCellID3 Watchdog PrimeCell Identification 3


Device Identification

Read-only registers in the system control module provide information about the MCU, such as version, part number, pin count, operating temperature range, and available peripherals on the device. The Device Identification 0 (DID0) and Device Identification 1 (DID1) registers provide details about the version, package, and temperature range of the device. The peripheral present registers starting at system control offset 0x300, such as the Watchdog Timer Peripheral Present (PPWD) register, provide information on how many of each type of module are included on the device. Finally, information about the capabilities of the on-chip peripherals are provided at offset 0xFC0 in the register space of each peripheral in the peripheral properties registers, such as the GPTM Peripheral Properties (GPTMPP). In addition, four unique identifier registers, Unique Identifier n (UNIQUEIDn), provide a 128-bit unique identifier that cannot be modified for each device.

JTAG Identification

Figure 6-3 shows the format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1. The major uses of the JTAG port are for manufacturer testing of component assembly and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x4BA0.0477. This value lets the debuggers automatically configure themselves to work correctly with the Cortex-M4F during debug.

MSP432E411Y idcode-register-format.gif Figure 6-3 IDCODE Register Format

ROM Version

The internal ROM is at address 0x0100.0000 of the device memory map.

Boot Modes

After POR and device initialization occurs, the hardware loads the stack pointer from either flash or ROM, based on the presence of an application in flash and the state of the EN bit in the BOOTCFG register.

If the flash address 0x0000.0004 contains an erased word (value 0xFFFF.FFFF) or the EN bit is of the BOOTCFG register is clear, the stack pointer and reset vector pointer are loaded from ROM at address 0x0100.0000 and 0x0100.0004, respectively. The bootloader executes and configures the available boot slave interfaces and waits for a programmer, host PC, or boot server to load its software. The bootloader uses a simple packet interface to provide synchronous communication with the device for I2C, SSI, and UART. The speed of the bootloader is determined by the frequency of the internal oscillator (PIOSC) or external crystal (if connected).

The ROM invokes the USB and Ethernet bootloader only when an external crystal is detected. Also, the Ethernet bootloader works only when a 25-MHz crystal is detected.

The following serial interfaces can be used:

  • UART0
  • SSI0
  • I2C0
  • USB
  • Ethernet MAC and Integrated PHY

If the check of the flash at address 0x0000.0004 contains a valid reset vector value and the EN bit in the BOOTCFG register is set, the stack pointer and reset vector values are fetched from the beginning of flash. This application stack pointer and reset vector are loaded and the processor executes the application directly. Otherwise, the stack pointer and reset vector values are fetched from the beginning of ROM.