JAJSEQ5A
August 2017 – February 2018
UCC24612
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
ハイサイドSRによるフライバック
ローサイドSRによるフライバック
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power Management
7.3.2
Synchronous Rectifier Control
7.3.3
Adaptive Blanking Time
7.3.3.1
Turn-On Blanking Timer (Minimum On Time)
7.3.3.2
Turn-Off Blanking Timer
7.3.3.3
SR Turn-on Re-arm
7.3.4
Gate Voltage Clamping
7.3.5
Standby Mode
7.4
Device Functional Modes
7.4.1
UVLO Mode
7.4.2
Standby Mode
7.4.3
Run Mode
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
SR MOSFET Selection
8.2.2.2
Bypass Capacitor Selection
8.2.2.3
Snubber design
8.2.2.4
High-Side Operation
8.2.3
Application Curves
8.2.3.1
Steady State Testing Low-Side Configuration
8.2.3.2
Steady State Testing High-Side Configuration
9
Power Supply Recommendations
10
PCB Layout
10.1
Layout Guidelines
10.2
Layout Example
11
デバイスおよびドキュメントのサポート
11.1
コミュニティ・リソース
11.2
商標
11.3
静電気放電に関する注意事項
11.4
Glossary
12
メカニカル、パッケージ、および注文情報
10.2
Layout Example
Figure 35.
PCB Layout for Driving an SR with SO-8 Package