JAJSF15P July   2006  – January 2025 TPD4E001

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—JEDEC Specification
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9.   Power Supply Recommendations
  10. Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  11. Device and Documentation Support
    1. 9.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

Pin Functions

PINI/ODESCRIPTION
NAMEDRS, DRL, DPKDBV, DCKTPD4E001R
GND325Ground
IOx111IESD-protected channel
233
444
566
VCC652IPower-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor
Exposed thermal
pad (DRS package only)
Exposed thermal pad. Connect to GND or leave floating