JAJSF78L June 2006 – May 2018 TPS65023 , TPS65023B
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VI | Input voltage range, VINDCDC2 | 2.5 | 6 | V | |||
IO | Maximum output current | DEFDCDC2 = GND | 1200 | mA | |||
VINDCDC2 = 3.6 V;
3.3 V - 1% ≤ VDCDC2 ≤ 3.3V + 1% |
1000 | ||||||
I(SD) | Shutdown supply current in VINDCDC2 | DCDC2_EN = GND | 0.1 | 1 | μA | ||
rDS(on) | P-channel MOSFET on-resistance | VINDCDC2 = V(GS) = 3.6 V | 140 | 300 | mΩ | ||
Ilkg | P-channel leakage current | VINDCDC2 = 6 V | 2 | μA | |||
rDS(on) | N-channel MOSFET on-resistance | VINDCDC2 = V(GS) = 3.6 V | 150 | 297 | mΩ | ||
Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | ||
ILIMF | Forward current limit (P-channel and N-channel) | 2.5 V < VINDCDC2 < 6 V | 1.74 | 1.94 | 2.12 | A | |
fS | Oscillator frequency | 1.95 | 2.25 | 2.55 | MHz | ||
Fixed output voltage FPWMDCDC2=0 | VDCDC2 = 1.8 V | VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.2 A |
–2% | 2% | |||
VDCDC2 = 3.3 V | VINDCDC2 = 3.7 V to 6 V;
0 mA ≤ IO ≤ 1.2 A |
–1% | 1% | ||||
Fixed output voltage FPWMDCDC2=1 | VDCDC2 = 1.8 V | VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.2 A |
–2% | 2% | |||
VDCDC2 = 3.3 V | VINDCDC2 = 3.7 V to 6 V;
0 mA ≤ IO ≤ 1.2 A |
–1% | 1% | ||||
Adjustable output voltage with resistor divider at DEFDCDC2 FPWMDCDC2=0 | VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1 A | –2% | 2% | ||||
Adjustable output voltage with resistor divider at DEFDCDC2; FPWMDCDC2=1 | VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1 A | –1% | 1% | ||||
Line Regulation | VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA | 0% | V | ||||
Load Regulation | IO = 10 mA to 1000 mA | 0.25% | A | ||||
tStart | Start-up time | Time from active EN to start switching | 145 | 175 | 200 | µs | |
tRamp | VOUT ramp-up time | Time to ramp from 5% to 95% of VOUT | 400 | 750 | 1000 | μs | |
Internal resistance from L2 to GND | 1 | MΩ | |||||
VDCDC2 discharge resistance | DCDC2 discharge =1 | 300 | Ω |