7.3.5 Output Overcurrent Limit and Undervoltage Protection

The output overcurrent limit (OCL) is implemented using a cycle by cycle valley detect control circuit. The switching current is monitored during off state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switching current. To improve accuracy, the voltage sensing is temperature compensated.

During the on-time of the high-side FET switch, the switching current increases at a linear rate determined by V_IN, V_OUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current I_OUT. If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.

There are some important considerations for this type of over current limit. When the load current is higher than the over current threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and the current is being limited, output voltage tends to drop because the load demand is higher than what the converter can support. When the output voltage falls below 65% of the target voltage, the UVP comparator detects it and shuts down the device after a deglitch wait time of 0.25ms and then re-start after the hiccup time of 25ms. When the over current condition is removed, the output will be recovered.