JAJSFU9C July   2018  – June 2025 ESD321

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 説明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings – JEDEC Specifications
    3. 5.3 ESD Ratings – IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Signal Range
        2. 7.2.2.2 Operating Frequency
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VRWMReverse stand-off voltageIIO < 50nA, across operating temperature range3.6V
ILEAKAGELeakage current at 3.6VVIO = 3.6V, I/O to GND0.110nA
VBRFBreakdown voltage, I/O to GND (1)IIO = 1mA4.57.5V
VFWDForward Voltage, GND to I/O (1)IIO = 1mA0.8V
VHOLDHolding voltage, I/O to GND (2)IIO = 1mA5.1V
VCLAMPClamping voltageIPP = 6A (8/20µs Surge), I/O to GND6.3V
IPP = 16A (100ns TLP), I/O to GND6.8V
IPP = 16A (100ns TLP), GND to I/O4.7V
RDYNDynamic resistanceI/O to GND, 100ns TLP, between 10 to 20A IPP0.13Ω
GND to I/O , 100ns TLP, between 10 to 20A IPP0.2
CLINELine capacitance, IO to GNDVIO = 0V, Vp-p = 30mV, f = 1MHz0.91.1pF
VBRF and VBRR are defined as the voltage obtained at 1mA when sweeping the voltage up, before the device latches into the snapback state
VHOLD is defined as the voltage when 1mA is applied, after the device has successfully latched into the snapback state.