JAJSH81B April   2019  – February 2021 TPS929120-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Bias and Power
        1. 7.3.1.1 Power Supply (SUPPLY)
        2. 7.3.1.2 5-V Low-Drop-Out Linear Regulator (VLDO)
        3. 7.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 7.3.1.4 Programmable Low Supply Warning
      2. 7.3.2 Constant Current Output
        1. 7.3.2.1 Reference Current With External Resistor (REF)
        2. 7.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 7.3.3 PWM Dimming
        1. 7.3.3.1 PWM Dimming Frequency
        2. 7.3.3.2 PWM Generator
        3. 7.3.3.3 Linear Brightness Control
        4. 7.3.3.4 Exponential Brightness Control
        5. 7.3.3.5 External Clock Input for PWM Generator (CLK)
        6. 7.3.3.6 External PWM Input ( PWM0 and PWM1)
      4. 7.3.4 On-chip 8-bit Analog-to-Digital Converter (ADC)
      5. 7.3.5 Diagnostic and Protection in Normal State
        1. 7.3.5.1  Fault Masking
        2. 7.3.5.2  Supply Undervoltage Lockout Diagnostics in Normal State
        3. 7.3.5.3  Low-Supply Warning Diagnostics in Normal State
        4. 7.3.5.4  Reference Diagnostics in Normal State
        5. 7.3.5.5  Pre-Thermal Warning and Overtemperature Protection in Normal State
        6. 7.3.5.6  Communication Loss Diagnostic in Normal State
        7. 7.3.5.7  LED Open-Circuit Diagnostics in Normal State
        8. 7.3.5.8  LED Short-circuit Diagnostics in Normal State
        9. 7.3.5.9  On-Demand Off-State Invisible Diagnostics
        10. 7.3.5.10 On-Demand Off-State Single-LED Short-Circuit (SS) Diagnostics
        11. 7.3.5.11 Automatic Single-LED Short-Circuit (AutoSS) Detection in Normal State
        12. 7.3.5.12 EEPROM CRC Error in Normal State
        13.       47
      6. 7.3.6 Diagnostic and Protection in Fail-Safe States
        1. 7.3.6.1 Fault Masking
        2. 7.3.6.2 Supply UVLO Diagnostics in Fail-Safe States
        3. 7.3.6.3 Low-supply Warning Diagnostics in Fail-Safe states
        4. 7.3.6.4 Reference Diagnostics at Fail-Safe States
        5. 7.3.6.5 Overtemperature Protection in Fail-Safe State
        6. 7.3.6.6 LED Open-circuit Diagnostics in Fail-Safe State
        7. 7.3.6.7 LED Short-circuit Diagnostics in Fail-safe State
        8. 7.3.6.8 EEPROM CRC Error in Fail-safe State
        9.       57
    4. 7.4 Device Functional Modes
      1. 7.4.1 POR State
      2. 7.4.2 Initialization State
      3. 7.4.3 Normal State
      4. 7.4.4 Fail-Safe States
      5. 7.4.5 Program State
      6. 7.4.6 Programmable Output Failure State
      7. 7.4.7 ERR Output
      8. 7.4.8 Register Default Data
    5. 7.5 Programming
      1. 7.5.1 FlexWire Protocol
        1. 7.5.1.1 Protocol Overview
        2. 7.5.1.2 UART Interface Address Setting
        3. 7.5.1.3 Status Response
        4. 7.5.1.4 Synchronization Byte
        5. 7.5.1.5 Device Address Byte
        6. 7.5.1.6 Register Address Byte
        7. 7.5.1.7 Data Frame
        8.       76
        9. 7.5.1.8 CRC Frame
        10. 7.5.1.9 Burst Mode
      2. 7.5.2 Registers Lock
      3. 7.5.3 All Registers CRC Check
      4. 7.5.4 EEPROM Programming
        1. 7.5.4.1 Chip Selection by Pulling REF Pin High
        2. 7.5.4.2 Chip Selection by ADDR Pins configuration
        3. 7.5.4.3 EEPROM Register Access and Burn
        4. 7.5.4.4 EEPROM Program State Exit
        5. 7.5.4.5 Reading Back EEPROM
    6. 7.6 Register Maps
      1. 7.6.1 FullMap Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Smart Rear Lamp With Distributed LED drivers
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

FullMap Registers

Table 7-14 lists the FullMap registers. All register offset addresses not listed in Table 7-14 should be considered as reserved locations and the register contents should not be modified.

Table 7-14 FULLMAP Registers
OffsetAcronymRegister NameSection
0hIOUT0Output Current Setting for CH0Go
1hIOUT1Output Current Setting for CH1Go
2hIOUT2Output Current Setting for CH2Go
3hIOUT3Output Current Setting for CH3Go
4hIOUT4Output Current Setting for CH4Go
5hIOUT5Output Current Setting for CH5Go
6hIOUT6Output Current Setting for CH6Go
7hIOUT7Output Current Setting for CH7Go
8hIOUT8Output Current Setting for CH8Go
9hIOUT9Output Current Setting for CH9Go
AhIOUT10Output Current Setting for CH10Go
BhIOUT11Output Current Setting for CH11Go
20hPWM0Output PWM Duty-cycle Setting for CH0Go
21hPWM1Output PWM Duty-cycle Setting for CH1Go
22hPWM2Output PWM Duty-cycle Setting for CH2Go
23hPWM3Output PWM Duty-cycle Setting for CH3Go
24hPWM4Output PWM Duty-cycle Setting for CH4Go
25hPWM5Output PWM Duty-cycle Setting for CH5Go
26hPWM6Output PWM Duty-cycle Setting for CH6Go
27hPWM7Output PWM Duty-cycle Setting for CH7Go
28hPWM8Output PWM Duty-cycle Setting for CH8Go
29hPWM9Output PWM Duty-cycle Setting for CH9Go
2AhPWM10Output PWM Duty-cycle Setting for CH10Go
2BhPWM11Output PWM Duty-cycle Setting for CH11Go
40hPWML0Output PWM Duty-cycle Setting Lower bits for CH0Go
41hPWML1Output PWM Duty-cycle Setting Lower bits for CH1Go
42hPWML2Output PWM Duty-cycle Setting Lower bits for CH2Go
43hPWML3Output PWM Duty-cycle Setting Lower bits for CH3Go
44hPWML4Output PWM Duty-cycle Setting Lower bits for CH4Go
45hPWML5Output PWM Duty-cycle Setting Lower bits for CH5Go
46hPWML6Output PWM Duty-cycle Setting Lower bits for CH6Go
47hPWML7Output PWM Duty-cycle Setting Lower bits for CH7Go
48hPWML8Output PWM Duty-cycle Setting Lower bits for CH8Go
49hPWML9Output PWM Duty-cycle Setting Lower bits for CH9Go
4AhPWML10Output PWM Duty-cycle Setting Lower bits for CH10Go
4BhPWML11Output PWM Duty-cycle Setting Lower bits for CH11Go
50hCONF_EN0Channel Enable Register 0Go
51hCONF_EN1Channel Enable Register 1Go
54hCONF_DIAGEN0Diagnostics Enable Register 0Go
55hCONF_DIAGEN1Diagnostics Enable Register 1Go
56hCONF_MISC0Miscellanous Register 0Go
57hCONF_MISC1Miscellanous Register 1Go
58hCONF_MISC2Miscellanous Register 2Go
59hCONF_MISC3Miscellanous Register 3Go
5AhCONF_MISC4Miscellanous Register 4Go
5BhCONF_MISC5Miscellanous Register 5Go
60hCLRConfiguration Register for ClearGo
61hCONF_LOCKConfiguration Register for LOCKGo
62hCONF_MISC6Miscellanous Register 6Go
63hCONF_MISC7Miscellanous Register 7Go
64hCONF_MISC8Miscellanous Register 8Go
65hCONF_MISC9Miscellanous Register 9Go
70hFLAG0Device status flag register 0Go
71hFLAG1Device status flag register 1Go
72hFLAG2Device status flag register 2Go
73hFLAG3Device status flag register 3Go
74hFLAG4Device status flag register 4Go
75hFLAG5Device status flag register 5Go
77hFLAG7Device status flag register 7Go
78hFLAG8Device status flag register 8Go
7BhFLAG11Device status flag register 11Go
7ChFLAG12Device status flag register 12Go
7DhFLAG13Device status flag register 13Go
7EhFLAG14Device status flag register 14Go
80hEEPI0EEPROM Output Current Setting for CH0Go
81hEEPI1EEPROM Output Current Setting for CH1Go
82hEEPI2EEPROM Output Current Setting for CH2Go
83hEEPI3EEPROM Output Current Setting for CH3Go
84hEEPI4EEPROM Output Current Setting for CH4Go
85hEEPI5EEPROM Output Current Setting for CH5Go
86hEEPI6EEPROM Output Current Setting for CH6Go
87hEEPI7EEPROM Output Current Setting for CH7Go
88hEEPI8EEPROM Output Current Setting for CH8Go
89hEEPI9EEPROM Output Current Setting for CH9Go
8AhEEPI10EEPROM Output Current Setting for CH10Go
8BhEEPI11EEPROM Output Current Setting for CH11Go
A0hEEPP0EEPROM Output PWM Duty-cycle Setting for CH0Go
A1hEEPP1EEPROM Output PWM Duty-cycle Setting for CH1Go
A2hEEPP2EEPROM Output PWM Duty-cycle Setting for CH2Go
A3hEEPP3EEPROM Output PWM Duty-cycle Setting for CH3Go
A4hEEPP4EEPROM Output PWM Duty-cycle Setting for CH4Go
A5hEEPP5EEPROM Output PWM Duty-cycle Setting for CH5Go
A6hEEPP6EEPROM Output PWM Duty-cycle Setting for CH6Go
A7hEEPP7EEPROM Output PWM Duty-cycle Setting for CH7Go
A8hEEPP8EEPROM Output PWM Duty-cycle Setting for CH8Go
A9hEEPP9EEPROM Output PWM Duty-cycle Setting for CH9Go
AAhEEPP10EEPROM Output PWM Duty-cycle Setting for CH10Go
ABhEEPP11EEPROM Output PWM Duty-cycle Setting for CH11Go
C0hEEPM0EEPROM Miscellaneous registers 0Go
C1hEEPM1EEPROM Miscellaneous registers 1Go
C2hEEPM2EEPROM Miscellaneous registers 2Go
C3hEEPM3EEPROM Miscellaneous registers 3Go
C4hEEPM4EEPROM Miscellaneous registers 4Go
C5hEEPM5EEPROM Miscellaneous registers 5Go
C6hEEPM6EEPROM Miscellaneous registers 6Go
C7hEEPM7EEPROM Miscellaneous registers 7Go
C8hEEPM8EEPROM Miscellaneous registers 8Go
C9hEEPM9EEPROM Miscellaneous registers 9Go
CAhEEPM10EEPROM Miscellaneous registers 10Go
CBhEEPM11EEPROM Miscellaneous registers 11Go
CFhEEPM15EEPROM CRC Check Value RegistersGo

Complex bit access types are encoded to fit into small table cells. Table 7-15 shows the codes that are used for access types in this section.

Table 7-15 FullMap Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1.1 IOUT0 Register (Offset = 0h) [reset = X]

IOUT0 is shown in Figure 7-19 and described in Table 7-16.

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Figure 7-19 IOUT0 Register
76543210
RESERVEDCONF_IOUT0
R-0hR/W-X
Table 7-16 IOUT0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT0R/WXOutput current setting for OUT0
Load EEPI0 data when reset

7.6.1.2 IOUT1 Register (Offset = 1h) [reset = X]

IOUT1 is shown in Figure 7-20 and described in Table 7-17.

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Figure 7-20 IOUT1 Register
76543210
RESERVEDCONF_IOUT1
R-0hR/W-X
Table 7-17 IOUT1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT1R/WXOutput current setting for OUT1
Load EEPI1 data when reset

7.6.1.3 IOUT2 Register (Offset = 2h) [reset = X]

IOUT2 is shown in Figure 7-21 and described in Table 7-18.

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Figure 7-21 IOUT2 Register
76543210
RESERVEDCONF_IOUT2
R-0hR/W-X
Table 7-18 IOUT2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT2R/WXOutput current setting for OUT2
Load EEPI2 data when reset

7.6.1.4 IOUT3 Register (Offset = 3h) [reset = X]

IOUT3 is shown in Figure 7-22 and described in Table 7-19.

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Figure 7-22 IOUT3 Register
76543210
RESERVEDCONF_IOUT3
R-0hR/W-X
Table 7-19 IOUT3 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT3R/WXOutput current setting for OUT3
Load EEPI3 data when reset

7.6.1.5 IOUT4 Register (Offset = 4h) [reset = X]

IOUT4 is shown in Figure 7-23 and described in Table 7-20.

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Figure 7-23 IOUT4 Register
76543210
RESERVEDCONF_IOUT4
R-0hR/W-X
Table 7-20 IOUT4 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT4R/WXOutput current setting for OUT4
Load EEPI4 data when reset

7.6.1.6 IOUT5 Register (Offset = 5h) [reset = X]

IOUT5 is shown in Figure 7-24 and described in Table 7-21.

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Figure 7-24 IOUT5 Register
76543210
RESERVEDCONF_IOUT5
R-0hR/W-X
Table 7-21 IOUT5 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT5R/WXOutput current setting for OUT5
Load EEPI5 data when reset

7.6.1.7 IOUT6 Register (Offset = 6h) [reset = X]

IOUT6 is shown in Figure 7-25 and described in Table 7-22.

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Figure 7-25 IOUT6 Register
76543210
RESERVEDCONF_IOUT6
R-0hR/W-X
Table 7-22 IOUT6 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT6R/WXOutput current setting for OUT6
Load EEPI6 data when reset

7.6.1.8 IOUT7 Register (Offset = 7h) [reset = X]

IOUT7 is shown in Figure 7-26 and described in Table 7-23.

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Figure 7-26 IOUT7 Register
76543210
RESERVEDCONF_IOUT7
R-0hR/W-X
Table 7-23 IOUT7 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT7R/WXOutput current setting for OUT7
Load EEPI7 data when reset

7.6.1.9 IOUT8 Register (Offset = 8h) [reset = X]

IOUT8 is shown in Figure 7-27 and described in Table 7-24.

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Figure 7-27 IOUT8 Register
76543210
RESERVEDCONF_IOUT8
R-0hR/W-X
Table 7-24 IOUT8 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT8R/WXOutput current setting for OUT8
Load EEPI8 data when reset

7.6.1.10 IOUT9 Register (Offset = 9h) [reset = X]

IOUT9 is shown in Figure 7-28 and described in Table 7-25.

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Figure 7-28 IOUT9 Register
76543210
RESERVEDCONF_IOUT9
R-0hR/W-X
Table 7-25 IOUT9 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT9R/WXOutput current setting for OUT9
Load EEPI9 data when reset

7.6.1.11 IOUT10 Register (Offset = Ah) [reset = X]

IOUT10 is shown in Figure 7-29 and described in Table 7-26.

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Figure 7-29 IOUT10 Register
76543210
RESERVEDCONF_IOUT10
R-0hR/W-X
Table 7-26 IOUT10 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT10R/WXOutput current setting for OUT10
Load EEPI10 data when reset

7.6.1.12 IOUT11 Register (Offset = Bh) [reset = X]

IOUT11 is shown in Figure 7-30 and described in Table 7-27.

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Figure 7-30 IOUT11 Register
76543210
RESERVEDCONF_IOUT11
R-0hR/W-X
Table 7-27 IOUT11 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0CONF_IOUT11R/WXOutput current setting for OUT11
Load EEPI11 data when reset

7.6.1.13 PWM0 Register (Offset = 20h) [reset = X]

PWM0 is shown in Figure 7-31 and described in Table 7-28.

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Figure 7-31 PWM0 Register
76543210
CONF_PWMOUT0
R/W-X
Table 7-28 PWM0 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT0R/WXPWM Dutycycle Register Setting for CH0
Load EEPP0 data when reset

7.6.1.14 PWM1 Register (Offset = 21h) [reset = X]

PWM1 is shown in Figure 7-32 and described in Table 7-29.

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Figure 7-32 PWM1 Register
76543210
CONF_PWMOUT1
R/W-X
Table 7-29 PWM1 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT1R/WXPWM Dutycycle Register Setting for CH1
Load EEPP1 data when reset

7.6.1.15 PWM2 Register (Offset = 22h) [reset = X]

PWM2 is shown in Figure 7-33 and described in Table 7-30.

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Figure 7-33 PWM2 Register
76543210
CONF_PWMOUT2
R/W-X
Table 7-30 PWM2 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT2R/WXPWM Dutycycle Register Setting for CH2
Load EEPP2 data when reset

7.6.1.16 PWM3 Register (Offset = 23h) [reset = X]

PWM3 is shown in Figure 7-34 and described in Table 7-31.

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Figure 7-34 PWM3 Register
76543210
CONF_PWMOUT3
R/W-X
Table 7-31 PWM3 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT3R/WXPWM Dutycycle Register Setting for CH3
Load EEPP3 data when reset

7.6.1.17 PWM4 Register (Offset = 24h) [reset = X]

PWM4 is shown in Figure 7-35 and described in Table 7-32.

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Figure 7-35 PWM4 Register
76543210
CONF_PWMOUT4
R/W-X
Table 7-32 PWM4 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT4R/WXPWM Dutycycle Register Setting for CH4
Load EEPP4 data when reset

7.6.1.18 PWM5 Register (Offset = 25h) [reset = X]

PWM5 is shown in Figure 7-36 and described in Table 7-33.

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Figure 7-36 PWM5 Register
76543210
CONF_PWMOUT5
R/W-X
Table 7-33 PWM5 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT5R/WXPWM Dutycycle Register Setting for CH5
Load EEPP5 data when reset

7.6.1.19 PWM6 Register (Offset = 26h) [reset = X]

PWM6 is shown in Figure 7-37 and described in Table 7-34.

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Figure 7-37 PWM6 Register
76543210
CONF_PWMOUT6
R/W-X
Table 7-34 PWM6 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT6R/WXPWM Dutycycle Register Setting for CH6
Load EEPP6 data when reset

7.6.1.20 PWM7 Register (Offset = 27h) [reset = X]

PWM7 is shown in Figure 7-38 and described in Table 7-35.

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Figure 7-38 PWM7 Register
76543210
CONF_PWMOUT7
R/W-X
Table 7-35 PWM7 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT7R/WXPWM Dutycycle Register Setting for CH7
Load EEPP7 data when reset

7.6.1.21 PWM8 Register (Offset = 28h) [reset = X]

PWM8 is shown in Figure 7-39 and described in Table 7-36.

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Figure 7-39 PWM8 Register
76543210
CONF_PWMOUT8
R/W-X
Table 7-36 PWM8 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT8R/WXPWM Dutycycle Register Setting for CH8
Load EEPP8 data when reset

7.6.1.22 PWM9 Register (Offset = 29h) [reset = X]

PWM9 is shown in Figure 7-40 and described in Table 7-37.

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Figure 7-40 PWM9 Register
76543210
CONF_PWMOUT9
R/W-X
Table 7-37 PWM9 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT9R/WXPWM Dutycycle Register Setting for CH9
Load EEPP9 data when reset

7.6.1.23 PWM10 Register (Offset = 2Ah) [reset = X]

PWM10 is shown in Figure 7-41 and described in Table 7-38.

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Figure 7-41 PWM10 Register
76543210
CONF_PWMOUT10
R/W-X
Table 7-38 PWM10 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT10R/WXPWM Dutycycle Register Setting for CH10
Load EEPP10 data when reset

7.6.1.24 PWM11 Register (Offset = 2Bh) [reset = X]

PWM11 is shown in Figure 7-42 and described in Table 7-39.

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Figure 7-42 PWM11 Register
76543210
CONF_PWMOUT11
R/W-X
Table 7-39 PWM11 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_PWMOUT11R/WXPWM Dutycycle Register Setting for CH11
Load EEPP11 data when reset

7.6.1.25 PWML0 Register (Offset = 40h) [reset = Fh]

PWML0 is shown in Figure 7-43 and described in Table 7-40.

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Figure 7-43 PWML0 Register
76543210
RESERVEDCONF_PWMLOWOUT0
R-0hR/W-Fh
Table 7-40 PWML0 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT0R/WFhPWM Dutycycle Register Setting lower 4 bits for CH0

7.6.1.26 PWML1 Register (Offset = 41h) [reset = Fh]

PWML1 is shown in Figure 7-44 and described in Table 7-41.

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Figure 7-44 PWML1 Register
76543210
RESERVEDCONF_PWMLOWOUT1
R-0hR/W-Fh
Table 7-41 PWML1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT1R/WFhPWM Dutycycle Register Setting lower 4 bits for CH1

7.6.1.27 PWML2 Register (Offset = 42h) [reset = Fh]

PWML2 is shown in Figure 7-45 and described in Table 7-42.

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Figure 7-45 PWML2 Register
76543210
RESERVEDCONF_PWMLOWOUT2
R-0hR/W-Fh
Table 7-42 PWML2 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT2R/WFhPWM Dutycycle Register Setting lower 4 bits for CH2

7.6.1.28 PWML3 Register (Offset = 43h) [reset = Fh]

PWML3 is shown in Figure 7-46 and described in Table 7-43.

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Figure 7-46 PWML3 Register
76543210
RESERVEDCONF_PWMLOWOUT3
R-0hR/W-Fh
Table 7-43 PWML3 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT3R/WFhPWM Dutycycle Register Setting lower 4 bits for CH3

7.6.1.29 PWML4 Register (Offset = 44h) [reset = Fh]

PWML4 is shown in Figure 7-47 and described in Table 7-44.

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Figure 7-47 PWML4 Register
76543210
RESERVEDCONF_PWMLOWOUT4
R-0hR/W-Fh
Table 7-44 PWML4 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT4R/WFhPWM Dutycycle Register Setting lower 4 bits for CH4

7.6.1.30 PWML5 Register (Offset = 45h) [reset = Fh]

PWML5 is shown in Figure 7-48 and described in Table 7-45.

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Figure 7-48 PWML5 Register
76543210
RESERVEDCONF_PWMLOWOUT5
R-0hR/W-Fh
Table 7-45 PWML5 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT5R/WFhPWM Dutycycle Register Setting lower 4 bits for CH5

7.6.1.31 PWML6 Register (Offset = 46h) [reset = Fh]

PWML6 is shown in Figure 7-49 and described in Table 7-46.

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Figure 7-49 PWML6 Register
76543210
RESERVEDCONF_PWMLOWOUT6
R-0hR/W-Fh
Table 7-46 PWML6 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT6R/WFhPWM Dutycycle Register Setting lower 4 bits for CH6

7.6.1.32 PWML7 Register (Offset = 47h) [reset = Fh]

PWML7 is shown in Figure 7-50 and described in Table 7-47.

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Figure 7-50 PWML7 Register
76543210
RESERVEDCONF_PWMLOWOUT7
R-0hR/W-Fh
Table 7-47 PWML7 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT7R/WFhPWM Dutycycle Register Setting lower 4 bits for CH7

7.6.1.33 PWML8 Register (Offset = 48h) [reset = Fh]

PWML8 is shown in Figure 7-51 and described in Table 7-48.

Return to the Summary Table.

Figure 7-51 PWML8 Register
76543210
RESERVEDCONF_PWMLOWOUT8
R-0hR/W-Fh
Table 7-48 PWML8 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT8R/WFhPWM Dutycycle Register Setting lower 4 bits for CH8

7.6.1.34 PWML9 Register (Offset = 49h) [reset = Fh]

PWML9 is shown in Figure 7-52 and described in Table 7-49.

Return to the Summary Table.

Figure 7-52 PWML9 Register
76543210
RESERVEDCONF_PWMLOWOUT9
R-0hR/W-Fh
Table 7-49 PWML9 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT9R/WFhPWM Dutycycle Register Setting lower 4 bits for CH9

7.6.1.35 PWML10 Register (Offset = 4Ah) [reset = Fh]

PWML10 is shown in Figure 7-53 and described in Table 7-50.

Return to the Summary Table.

Figure 7-53 PWML10 Register
76543210
RESERVEDCONF_PWMLOWOUT10
R-0hR/W-Fh
Table 7-50 PWML10 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT10R/WFhPWM Dutycycle Register Setting lower 4 bits for CH10

7.6.1.36 PWML11 Register (Offset = 4Bh) [reset = Fh]

PWML11 is shown in Figure 7-54 and described in Table 7-51.

Return to the Summary Table.

Figure 7-54 PWML11 Register
76543210
RESERVEDCONF_PWMLOWOUT11
R-0hR/W-Fh
Table 7-51 PWML11 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3-0CONF_PWMLOWOUT11R/WFhPWM Dutycycle Register Setting lower 4 bits for CH11

7.6.1.37 CONF_EN0 Register (Offset = 50h) [reset = 0h]

CONF_EN0 is shown in Figure 7-55 and described in Table 7-52.

Return to the Summary Table.

Channel enable settings for channel 0 to 7.

Figure 7-55 CONF_EN0 Register
76543210
CONF_ENCH7CONF_ENCH6CONF_ENCH5CONF_ENCH4CONF_ENCH3CONF_ENCH2CONF_ENCH1CONF_ENCH0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-52 CONF_EN0 Register Field Descriptions
BitFieldTypeResetDescription
7CONF_ENCH7R/W0hChannel 7 enable register.

0h = Disabled

1h = Enabled

6CONF_ENCH6R/W0hChannel 6 enable register.

0h = Disabled

1h = Enabled

5CONF_ENCH5R/W0hChannel 5 enable register.

0h = Disabled

1h = Enabled

4CONF_ENCH4R/W0hChannel 4 enable register.

0h = Disabled

1h = Enabled

3CONF_ENCH3R/W0hChannel 3 enable register.

0h = Disabled

1h = Enabled

2CONF_ENCH2R/W0hChannel 2 enable register.

0h = Disabled

1h = Enabled

1CONF_ENCH1R/W0hChannel 1 enable register.

0h = Disabled

1h = Enabled

0CONF_ENCH0R/W0hChannel 0 enable register.

0h = Disabled

1h = Enabled

7.6.1.38 CONF_EN1 Register (Offset = 51h) [reset = 0h]

CONF_EN1 is shown in Figure 7-56 and described in Table 7-53.

Return to the Summary Table.

Channel enable settings for channel 8 to 11.

Figure 7-56 CONF_EN1 Register
76543210
RESERVEDCONF_ENCH11CONF_ENCH10CONF_ENCH9CONF_ENCH8
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-53 CONF_EN1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3CONF_ENCH11R/W0hChannel 11 enable register.

0h = Disabled

1h = Enabled

2CONF_ENCH10R/W0hChannel 10 enable register.

0h = Disabled

1h = Enabled

1CONF_ENCH9R/W0hChannel 9 enable register.

0h = Disabled

1h = Enabled

0CONF_ENCH8R/W0hChannel 8 enable register.

0h = Disabled

1h = Enabled

7.6.1.39 CONF_DIAGEN0 Register (Offset = 54h) [reset = X]

CONF_DIAGEN0 is shown in Figure 7-57 and described in Table 7-54.

Return to the Summary Table.

Output diagnostics enable settings for channel 0 to 7.

Figure 7-57 CONF_DIAGEN0 Register
76543210
CONF_DIAGENCH7CONF_DIAGENCH6CONF_DIAGENCH5CONF_DIAGENCH4CONF_DIAGENCH3CONF_DIAGENCH2CONF_DIAGENCH1CONF_DIAGENCH0
R/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-XR/W-X
Table 7-54 CONF_DIAGEN0 Register Field Descriptions
BitFieldTypeResetDescription
7CONF_DIAGENCH7R/WXChannel 7 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH7 code when reset

6CONF_DIAGENCH6R/WXChannel 6 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH6 code when reset

5CONF_DIAGENCH5R/WXChannel 5 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH5 code when reset

4CONF_DIAGENCH4R/WXChannel 4 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH4 code when reset

3CONF_DIAGENCH3R/WXChannel 3 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH3 code when reset

2CONF_DIAGENCH2R/WXChannel 2 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH2 code when reset

1CONF_DIAGENCH1R/WXChannel 1 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH1 code when reset

0CONF_DIAGENCH0R/WXChannel 0 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH0 code when reset

7.6.1.40 CONF_DIAGEN1 Register (Offset = 55h) [reset = X]

CONF_DIAGEN1 is shown in Figure 7-58 and described in Table 7-55.

Return to the Summary Table.

Output diagnostics enable settings for channel 8 to 11.

Figure 7-58 CONF_DIAGEN1 Register
76543210
RESERVEDCONF_DIAGENCH11CONF_DIAGENCH10CONF_DIAGENCH9CONF_DIAGENCH8
R-0hR/W-XR/W-XR/W-XR/W-X
Table 7-55 CONF_DIAGEN1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3CONF_DIAGENCH11R/WXChannel 11 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH11 code when reset

2CONF_DIAGENCH10R/WXChannel 10 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH10 code when reset

1CONF_DIAGENCH9R/WXChannel 9 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH9 code when reset

0CONF_DIAGENCH8R/WXChannel 8 diagnostics enable register.

0h = Disabled

1h = Enabled
Load EEP_DIAGENCH8 code when reset

7.6.1.41 CONF_MISC0 Register (Offset = 56h) [reset = X]

CONF_MISC0 is shown in Figure 7-59 and described in Table 7-56.

Return to the Summary Table.

Figure 7-59 CONF_MISC0 Register
76543210
CONF_AUTOSSCONF_LDORESERVEDCONF_EXPENRESERVED
R/W-0hR/W-XR-0hR/W-XR/W-0h
Table 7-56 CONF_MISC0 Register Field Descriptions
BitFieldTypeResetDescription
7CONF_AUTOSSR/W0hAuto single-LED short-circuit configuration.

0h = Disabled

1h = Enabled

6CONF_LDOR/WXLDO output voltage setting.

0h = 5.0V

1h = 4.4V
Load EEP_LDO code when reset

5RESERVEDR0hRESERVED
4CONF_EXPENR/WXPWM exponetinal dimming enable register.

0h = Disabled

1h = Enabled
Load EEP_EXPEN code when reset

3-0RESERVEDR/W0hRESERVED

7.6.1.42 CONF_MISC1 Register (Offset = 57h) [reset = X]

CONF_MISC1 is shown in Figure 7-60 and described in Table 7-57.

Return to the Summary Table.

Figure 7-60 CONF_MISC1 Register
76543210
CONF_PWMFREQRESERVEDCONF_REFRANGE
R/W-XR-0hR/W-X
Table 7-57 CONF_MISC1 Register Field Descriptions
BitFieldTypeResetDescription
7-4CONF_PWMFREQR/WXPWM frequency selection register

0h = 200 Hz

1h = 250 Hz

2h = 300 Hz

3h = 350 Hz

4h = 400 Hz

5h = 500 Hz

6h = 600 Hz

7h = 800 Hz

8h = 1000 Hz

9h = 1200 Hz

Ah = 2 kHz

Bh = 4 kHz

Ch = 5.9 kHz

Dh = 7.8 kHz

Eh = 9.6 kHz

Fh = 20.8 kHz
Load EEP_PWMFREQ data when reset

3-2RESERVEDR0hRESERVED
1-0CONF_REFRANGER/WXReference current ratio setting register

0h = 64

1h = 128

2h = 256

3h = 512
Load EEP_REFRANGE data when reset

7.6.1.43 CONF_MISC2 Register (Offset = 58h) [reset = X]

CONF_MISC2 is shown in Figure 7-61 and described in Table 7-58.

Return to the Summary Table.

Figure 7-61 CONF_MISC2 Register
76543210
RESERVEDCONF_FLTIMEOUTCONF_ADCLOWSUPTH
R-0hR/W-XR/W-X
Table 7-58 CONF_MISC2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0hRESERVED
6-4CONF_FLTIMEOUTR/WXFlexWire timeout timer setting register.

0h = 1 ms

1h = 125 µs

2h = 250 µs

3h = 500 µs

4h = 1.25 ms

5h = 2.5 ms

6h = 5 ms

7h = 10 ms
Load EEP_FLTIMEOUT data when reset

3-0CONF_ADCLOWSUPTHR/WXADC Supply monitor threshold setting register.

0h = 5 V

1h = 6 V

2h = 7 V

3h = 8 V

4h = 9 V

5h = 10 V

6h = 11 V

7h = 12 V

8h = 13 V

9h = 14 V

Ah = 15 V

Bh = 16 V

Ch = 17 V

Dh = 18 V

Eh = 19 V

Fh = 20 V
Load EEP_ADCLOWSUPTH data when reset

7.6.1.44 CONF_MISC3 Register (Offset = 59h) [reset = X]

CONF_MISC3 is shown in Figure 7-62 and described in Table 7-59.

Return to the Summary Table.

Figure 7-62 CONF_MISC3 Register
76543210
CONF_ODIOUTCONF_ODPW
R/W-XR/W-X
Table 7-59 CONF_MISC3 Register Field Descriptions
BitFieldTypeResetDescription
7-4CONF_ODIOUTR/WXOn-demand diagnostics output current setting register.
0x0 to 0xE: IOUT = (CONF_ODIOUT*4+1)/64*I(FULL_RANGE)
0xF: ODIOUT is using its channel setting current
Load EEP_ODIOUT data when reset
3-0CONF_ODPWR/WXOn-demand diagnostics pulse-width setting EEPROM register.

0h = 100 µs

1h = 20 µs

2h = 30 µs

3h = 50 µs

4h = 80 µs

5h = 150 µs

6h = 200 µs

7h = 300 µs

8h = 500 µs

9h = 800 µs

Ah = 1 ms

Bh = 1.2 ms

Ch = 1.5 ms

Dh = 2 ms

Eh = 3 ms

Fh = 5 ms
Load EEP_ODPW data when reset

7.6.1.45 CONF_MISC4 Register (Offset = 5Ah) [reset = X]

CONF_MISC4 is shown in Figure 7-63 and described in Table 7-60.

Return to the Summary Table.

Figure 7-63 CONF_MISC4 Register
76543210
CONF_WDTIMERRESERVED
R/W-XR-0h
Table 7-60 CONF_MISC4 Register Field Descriptions
BitFieldTypeResetDescription
7-4CONF_WDTIMERR/WXWatchdog timer setting EEPROM register.

0h = Disabled, do not automatically enter fail-safe state

1h = 200 µs

2h = 500 µs

3h = 1 ms

4h = 2 ms

5h = 5 ms

6h = 10 ms

7h = 20 ms

8h = 50 ms

9h = 100 ms

Ah = 200 ms

Bh = 500 ms

Ch = 0 µs; direct enter fail-safe state

Dh = 0 µs; direct enter fail-safe state

Eh = 0 µs; direct enter fail-safe state

Fh = 0 µs; direct enter fail-safe state
Load EEP_WDTIMER data when reset

3-0RESERVEDR0hRESERVED

7.6.1.46 CONF_MISC5 Register (Offset = 5Bh) [reset = X]

CONF_MISC5 is shown in Figure 7-64 and described in Table 7-61.

Return to the Summary Table.

Figure 7-64 CONF_MISC5 Register
76543210
CONF_ADCSHORTTH
R/W-X
Table 7-61 CONF_MISC5 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_ADCSHORTTHR/WXADC short detection threshold setting register.
Load EEP_ADCSHORTTH data when rest

7.6.1.47 CLR Register (Offset = 60h) [reset = 0h]

CLR is shown in Figure 7-65 and described in Table 7-62.

Return to the Summary Table.

Configuration register for register clear and state configuration

Figure 7-65 CLR Register
76543210
RESERVEDCONF_FORCEFSCLR_REGCONF_FORCEERRCLR_FSCLR_FAULTCLR_POR
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-62 CLR Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5CONF_FORCEFSR/W0hWrite 1 to force device into Fail-safe state from normal state, automatically reset to 0.
4CLR_REGR/W0hWrite 1 to clear device register settings to default values, automatically reset to 0.
3CONF_FORCEERRR/W0hWrite 1 to force error setting register, automatically reset to 0.
0x0: ERR output = HIGH
0x1: ERR output = LOW;
2CLR_FSR/W0hWrite to force the device out of Fail-safe states to normal state, automatically reset to 0.
1CLR_FAULTR/W0hWrite 1 to clear all fault flags, automatically reset to 0.
0CLR_PORR/W0hWrite 1 to clear POR flag, automatically reset to 0.

7.6.1.48 CONF_LOCK Register (Offset = 61h) [reset = Fh]

CONF_LOCK is shown in Figure 7-66 and described in Table 7-63.

Return to the Summary Table.

Configuration register for register lock configuration

Figure 7-66 CONF_LOCK Register
76543210
RESERVEDCONF_CLRLOCKCONF_CONFLOCKCONF_IOUTLOCKCONF_PWMLOCK
R-0hR/W-1hR/W-1hR/W-1hR/W-1h
Table 7-63 CONF_LOCK Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3CONF_CLRLOCKR/W1hCLR register (address 60h) lock bit
0x0: CLR register write-protect disabled.
0x1: CLR register write-protected enabled.
2CONF_CONFLOCKR/W1hConfiguration (CONF_x) registers lock bit
0x0: Configuration setting register write-protect disabled
0x1: Configuration setting register write-protected enabled
1CONF_IOUTLOCKR/W1hIOUT registers (CONF_IOUTx) lock bit
0x0: Output current setting register write-protect disabled
0x1: Output current setting register write-protected enabled.
0CONF_PWMLOCKR/W1hPMW dutycyle registers (CONF_PWMOUTx+CONF_PWMLOWOUTx) lock bit
0x0: PWM Register write-protect disabled
0x1: PWM Register write-protected enabled.

7.6.1.49 CONF_MISC6 Register (Offset = 62h) [reset = 0h]

CONF_MISC6 is shown in Figure 7-67 and described in Table 7-64.

Return to the Summary Table.

Figure 7-67 CONF_MISC6 Register
76543210
CONF_STAYINEEPCONF_EEPREADBACKRESERVEDCONF_ADCCH
R/W-0hR/W-0hR-0hR/W-0h
Table 7-64 CONF_MISC6 Register Field Descriptions
BitFieldTypeResetDescription
7CONF_STAYINEEPR/W0hStay in EEPROM state setting.

0h = EEPROM mode disabled

1h = EEPROM mode enableds

6CONF_EEPREADBACKR/W0hSetting this bit allow EEPROM to overwrite configuration registers. Automatically returns to 0.
5RESERVEDR0hRESERVED
4-0CONF_ADCCHR/W0hADC Channel Selection Register, write this channel will automatically initiate ADC conversion.

7.6.1.50 CONF_MISC7 Register (Offset = 63h) [reset = 0h]

CONF_MISC7 is shown in Figure 7-68 and described in Table 7-65.

Return to the Summary Table.

Figure 7-68 CONF_MISC7 Register
76543210
RESERVEDCONF_EXTCLKCONF_SHAREPWMRESERVEDCONF_READSHADOWCONF_EEPMODE
R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
Table 7-65 CONF_MISC7 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hReserved
5CONF_EXTCLKR/W0hExternal CLK selection
0x0: Use internal clock source for PWM generator
0x1: Use external clock source for PWM generator
4CONF_SHAREPWMR/W0hSetting all channel PWM dutycycle to be same as CH0
0x0: All channel PWM dutycycle is set independently
0x1: All channel PWM dutycycle is the same as CH0
3-2RESERVEDR0hReserved
1CONF_READSHADOWR/W0hSetting EEPROM read back source.
0x0: From EEPROM
0x1: From EEPROM shadow registers
0CONF_EEPMODER/W0hEEPROM Programming State Setting.
0x0: Disable EEPMODE Programming State
0x1: Enable EEPMODE Programming State

7.6.1.51 CONF_MISC8 Register (Offset = 64h) [reset = 0h]

CONF_MISC8 is shown in Figure 7-69 and described in Table 7-66.

Return to the Summary Table.

Figure 7-69 CONF_MISC8 Register
76543210
CONF_MASKREFCONF_MASKCRCCONF_MASKSHORTCONF_MASKOPENCONF_MASKTSDCONF_EEPPROGCONF_SSSTARTCONF_INVDIAGSTART
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-66 CONF_MISC8 Register Field Descriptions
BitFieldTypeResetDescription
7CONF_MASKREFR/W0hReference fault mask register.
0x0: Reference fault will be reported to ERR output
0x1: Reference fault will not be reported to ERR output
6CONF_MASKCRCR/W0hCRC fault mask register.
0x0: CRC fault will be reported to ERR output
0x1: CRC fault will not be reported to ERR output
5CONF_MASKSHORTR/W0hSHORT fault mask register.
0x0: Short-circuit fault will be reported to ERR output.
0x1: Short-circuit fault will not be reported to ERR output;
4CONF_MASKOPENR/W0hOPEN fault mask register.
0x0: Open-circuit fault will be reported to ERR output
0x1: Open-circuit fault will not be reported to ERR output
3CONF_MASKTSDR/W0hOver temperature shutdown mask to ERR output.
0x0: TSD Fault unmasked to ERR output
0x1: TSD Fault masked to ERR output, output will be shutdown
2CONF_EEPPROGR/W0hEEPROM burning start in EEPROM mode only, automatically returns to 0
1CONF_SSSTARTR/W0hSingle LED Short diagnostics start, automatically returns to 0
0CONF_INVDIAGSTARTR/W0hInvisible Diagnostics start, automatically returns to 0

7.6.1.52 CONF_MISC9 Register (Offset = 65h) [reset = 0h]

CONF_MISC9 is shown in Figure 7-70 and described in Table 7-67.

Return to the Summary Table.

Figure 7-70 CONF_MISC9 Register
76543210
CONF_EEPGATE
R/W-0h
Table 7-67 CONF_MISC9 Register Field Descriptions
BitFieldTypeResetDescription
7-0CONF_EEPGATER/W0hEEPROM Gate for Access Password

7.6.1.53 FLAG0 Register (Offset = 70h) [reset = 3h]

FLAG0 is shown in Figure 7-71 and described in Table 7-68.

Return to the Summary Table.

Users read this register to understand if the device is working properly. It includes general fault flags, power, temperature, output failures.

Figure 7-71 FLAG0 Register
76543210
RESERVEDFLAG_REFFLAG_FSFLAG_OUTFLAG_PRETSDFLAG_TSDFLAG_PORFLAG_ERR
R-0hR-0hR-0hR-0hR-0hR-0hR-1hR-1h
Table 7-68 FLAG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0hRESERVED
6FLAG_REFR0hReference fault flag.
0x0: No reference fault is detected.
0x1: Device has reference fault.
5FLAG_FSR0hFail-safe flag.
0x0: Device is not in fail-safe mode.
0x1: Device is in fail-safe mode.
4FLAG_OUTR0hOutput fault flag.
0x0: No fault is detected on output channels.
0x1: Device has at least one fault detected on output channels.
3FLAG_PRETSDR0hOvertemperature pre-shut down flag.
0x0: No over-temperature pre-shutdown is detected.
0x1: Device has triggered over temperature pre-shutdown threshold.
2FLAG_TSDR0hOvertemperature shut down flag.
0x0: No over-temperature shutdown is detected.
0x1: Device has triggered over temperature shutdown.
1FLAG_PORR1hPower-on-reset flag.
0x0: No power-on-reset
0x1: Power-on-reset triggered
Write 1 to CLEAR_POR will clear the bit
0FLAG_ERRR1hError output flag.
0x0: No error flag
0x1: Device has at least one error flag

7.6.1.54 FLAG1 Register (Offset = 71h) [reset = X]

FLAG1 is shown in Figure 7-72 and described in Table 7-69.

Return to the Summary Table.

Users read this register to understand if the device is working properly. It includes general fault flags, power, temperature, output failures.

Figure 7-72 FLAG1 Register
76543210
RESERVEDFLAG_EXTFSFLAG_PROGREADYFLAG_ADCLOWSUPFLAG_ADCDONEFLAG_ODREADYFLAG_EEPCRC
R-0hR-XR-0hR-0hR-0hR-0hR-X
Table 7-69 FLAG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5FLAG_EXTFSRXFS pin voltage indicator
0x0: FS pin voltage is logic low
0x1: FS pin voltage is logic high
4FLAG_PROGREADYR0hEEPROM burning completion flag.
0x0: EEPROM burning not completed or not started
0x1: EEPROM burning completed
3FLAG_ADCLOWSUPR0hFlag for low supply voltage detection.
0x0: Supply is above preset ADC threshold
0x1: Supply has dropped below preset ADC threshold.
2FLAG_ADCDONER0hFlag for ADC conversion completition.
0x0: ADC data not available.
0x1: ADC data available with conversion completed, read ADC_OUT to clear FLAG_ADCDONE.
1FLAG_ODREADYR0hFlag for on-demand diagnostics.
0x0: on-demand diagnostics not completed or not started.
0x1: on-demand diagnostics completed.
0FLAG_EEPCRCRXFlag for EEPROM CRC check failure.
0x0: EEPROM CRC passes
0x1: EEPROM CRC check fails

7.6.1.55 FLAG2 Register (Offset = 72h) [reset = X]

FLAG2 is shown in Figure 7-73 and described in Table 7-70.

Return to the Summary Table.

ADC conversion output register for supply

Figure 7-73 FLAG2 Register
76543210
ADC_SUPPLY
R-X
Table 7-70 FLAG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0ADC_SUPPLYRXADC conversion output register for supply

7.6.1.56 FLAG3 Register (Offset = 73h) [reset = 0h]

FLAG3 is shown in Figure 7-74 and described in Table 7-71.

Return to the Summary Table.

ADC Conversion Output

Figure 7-74 FLAG3 Register
76543210
ADC_OUT
R-0h
Table 7-71 FLAG3 Register Field Descriptions
BitFieldTypeResetDescription
7-0ADC_OUTR0hADC Conversion output register

7.6.1.57 FLAG4 Register (Offset = 74h) [reset = 0h]

FLAG4 is shown in Figure 7-75 and described in Table 7-72.

Return to the Summary Table.

Users read this register to understand if there is any LED open-circuit, LED short-circuit or Single-LED short-circuit fault detected after on-demand diagnostics.

Figure 7-75 FLAG4 Register
76543210
FLAG_ODDIAGCH7FLAG_ODDIAGCH6FLAG_ODDIAGCH5FLAG_ODDIAGCH4FLAG_ODDIAGCH3FLAG_ODDIAGCH2FLAG_ODDIAGCH1FLAG_ODDIAGCH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 7-72 FLAG4 Register Field Descriptions
BitFieldTypeResetDescription
7FLAG_ODDIAGCH7R0hChannel 7 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
6FLAG_ODDIAGCH6R0hChannel 6 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
5FLAG_ODDIAGCH5R0hChannel 5 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
4FLAG_ODDIAGCH4R0hChannel 4 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
3FLAG_ODDIAGCH3R0hChannel 3 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
2FLAG_ODDIAGCH2R0hChannel 2 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
1FLAG_ODDIAGCH1R0hChannel 1 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
0FLAG_ODDIAGCH0R0hChannel 0 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected

7.6.1.58 FLAG5 Register (Offset = 75h) [reset = 0h]

FLAG5 is shown in Figure 7-76 and described in Table 7-73.

Return to the Summary Table.

Users read this register to understand if there is any LED open-circuit, LED short-circuit or Single-LED short-circuit fault detected after on-demand diagnostics.

Figure 7-76 FLAG5 Register
76543210
RESERVEDFLAG_ODDIAGCH11FLAG_ODDIAGCH10FLAG_ODDIAGCH9FLAG_ODDIAGCH8
R-0hR-0hR-0hR-0hR-0h
Table 7-73 FLAG5 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3FLAG_ODDIAGCH11R0hChannel 11 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
2FLAG_ODDIAGCH10R0hChannel 10 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
1FLAG_ODDIAGCH9R0hChannel 9 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected
0FLAG_ODDIAGCH8R0hChannel 8 on-demand diagnostics fault flag bit.
0x0: on-demand diagnostics fault not detected
0x1: on-demand diagnostics fault detected

7.6.1.59 FLAG7 Register (Offset = 77h) [reset = EFh]

FLAG7 is shown in Figure 7-77 and described in Table 7-74.

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EEPROM CRC check reference should be burnt in the end of production line if any EEPROM register is changed.

Figure 7-77 FLAG7 Register
76543210
CALC_EEPCRC
R-B3h
Table 7-74 FLAG7 Register Field Descriptions
BitFieldTypeResetDescription
7-0CALC_EEPCRCRB3hEEPROM CRC reference

Reset value is 09h for TPS929120A version

7.6.1.60 FLAG8 Register (Offset = 78h) [reset = X]

FLAG8 is shown in Figure 7-78 and described in Table 7-75.

Return to the Summary Table.

Calculated CRC result

Figure 7-78 FLAG8 Register
76543210
CALC_CONFCRC
R-X
Table 7-75 FLAG8 Register Field Descriptions
BitFieldTypeResetDescription
7-0CALC_CONFCRCRXCalculated CRC result for all CONFx registers

7.6.1.61 FLAG11 Register (Offset = 7Bh) [reset = 0h]

FLAG11 is shown in Figure 7-79 and described in Table 7-76.

Return to the Summary Table.

Users read this register to understand if there is any LED open-circuit fault detected.

Figure 7-79 FLAG11 Register
76543210
FLAG_OPENCH7FLAG_OPENCH6FLAG_OPENCH5FLAG_OPENCH4FLAG_OPENCH3FLAG_OPENCH2FLAG_OPENCH1FLAG_OPENCH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 7-76 FLAG11 Register Field Descriptions
BitFieldTypeResetDescription
7FLAG_OPENCH7R0hChannel 7 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
6FLAG_OPENCH6R0hChannel 6 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
5FLAG_OPENCH5R0hChannel 5 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
4FLAG_OPENCH4R0hChannel 4 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
3FLAG_OPENCH3R0hChannel 3 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
2FLAG_OPENCH2R0hChannel 2 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
1FLAG_OPENCH1R0hChannel 1 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
0FLAG_OPENCH0R0hChannel 1 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected

7.6.1.62 FLAG12 Register (Offset = 7Ch) [reset = 0h]

FLAG12 is shown in Figure 7-80 and described in Table 7-77.

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Users read this register to understand if there is any LED open-circuit fault detected.

Figure 7-80 FLAG12 Register
76543210
RESERVEDFLAG_OPENCH11FLAG_OPENCH10FLAG_OPENCH9FLAG_OPENCH8
R-0hR-0hR-0hR-0hR-0h
Table 7-77 FLAG12 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3FLAG_OPENCH11R0hChannel 11 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
2FLAG_OPENCH10R0hChannel 10 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
1FLAG_OPENCH9R0hChannel 9 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected
0FLAG_OPENCH8R0hChannel 8 open-circuit fault flag bit.
0x0: open-circuit fault not detected
0x1: open-circuit fault detected

7.6.1.63 FLAG13 Register (Offset = 7Dh) [reset = 0h]

FLAG13 is shown in Figure 7-81 and described in Table 7-78.

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Users read this register to understand if there is any LED short-circuit fault detected.

Figure 7-81 FLAG13 Register
76543210
FLAG_SHORTCH7FLAG_SHORTCH6FLAG_SHORTCH5FLAG_SHORTCH4FLAG_SHORTCH3FLAG_SHORTCH2FLAG_SHORTCH1FLAG_SHORTCH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 7-78 FLAG13 Register Field Descriptions
BitFieldTypeResetDescription
7FLAG_SHORTCH7R0hChannel 7 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected
6FLAG_SHORTCH6R0hChannel 6 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected
5FLAG_SHORTCH5R0hChannel 5 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected
4FLAG_SHORTCH4R0hChannel 4 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected
3FLAG_SHORTCH3R0hChannel 3 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected
2FLAG_SHORTCH2R0hChannel 2 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected
1FLAG_SHORTCH1R0hChannel 1 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected
0FLAG_SHORTCH0R0hChannel 0 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected

7.6.1.64 FLAG14 Register (Offset = 7Eh) [reset = 0h]

FLAG14 is shown in Figure 7-82 and described in Table 7-79.

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Users read this register to understand if there is any LED short-circuit fault detected.

Figure 7-82 FLAG14 Register
76543210
RESERVEDFLAG_SHORTCH11FLAG_SHORTCH10FLAG_SHORTCH9FLAG_SHORTCH8
R-0hR-0hR-0hR-0hR-0h
Table 7-79 FLAG14 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3FLAG_SHORTCH11R0hChannel 11 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected
2FLAG_SHORTCH10R0hChannel 10 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected
1FLAG_SHORTCH9R0hChannel 9 short-circuit fault flag bit.
0b: short-circuit fault not detected
0x1: short-circuit fault detected
0FLAG_SHORTCH8R0hChannel 8 short-circuit fault flag bit.
0x0: short-circuit fault not detected
0x1: short-circuit fault detected

7.6.1.65 EEPI0 Register (Offset = 80h) [reset = 3Fh]

EEPI0 is shown in Figure 7-83 and described in Table 7-80.

Return to the Summary Table.

EEPROM Output Current Setting for CH0

Figure 7-83 EEPI0 Register
76543210
RESERVEDEEP_IOUT0
R-0hR/W-3Fh
Table 7-80 EEPI0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT0R/W3FhOutput current setting for OUT0

7.6.1.66 EEPI1 Register (Offset = 81h) [reset = 3Fh]

EEPI1 is shown in Figure 7-84 and described in Table 7-81.

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EEPROM Output Current Setting for CH1

Figure 7-84 EEPI1 Register
76543210
RESERVEDEEP_IOUT1
R-0hR/W-3Fh
Table 7-81 EEPI1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT1R/W3FhOutput current setting for OUT1

7.6.1.67 EEPI2 Register (Offset = 82h) [reset = 3Fh]

EEPI2 is shown in Figure 7-85 and described in Table 7-82.

Return to the Summary Table.

EEPROM Output Current Setting for CH2

Figure 7-85 EEPI2 Register
76543210
RESERVEDEEP_IOUT2
R-0hR/W-3Fh
Table 7-82 EEPI2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT2R/W3FhOutput current setting for OUT2

7.6.1.68 EEPI3 Register (Offset = 83h) [reset = 3Fh]

EEPI3 is shown in Figure 7-86 and described in Table 7-83.

Return to the Summary Table.

EEPROM Output Current Setting for CH3

Figure 7-86 EEPI3 Register
76543210
RESERVEDEEP_IOUT3
R-0hR/W-3Fh
Table 7-83 EEPI3 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT3R/W3FhOutput current setting for OUT3

7.6.1.69 EEPI4 Register (Offset = 84h) [reset = 3Fh]

EEPI4 is shown in Figure 7-87 and described in Table 7-84.

Return to the Summary Table.

EEPROM Output Current Setting for CH4

Figure 7-87 EEPI4 Register
76543210
RESERVEDEEP_IOUT4
R-0hR/W-3Fh
Table 7-84 EEPI4 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT4R/W3FhOutput current setting for OUT4

7.6.1.70 EEPI5 Register (Offset = 85h) [reset = 3Fh]

EEPI5 is shown in Figure 7-88 and described in Table 7-85.

Return to the Summary Table.

EEPROM Output Current Setting for CH5

Figure 7-88 EEPI5 Register
76543210
RESERVEDEEP_IOUT5
R-0hR/W-3Fh
Table 7-85 EEPI5 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT5R/W3FhOutput current setting for OUT5

7.6.1.71 EEPI6 Register (Offset = 86h) [reset = 3Fh]

EEPI6 is shown in Figure 7-89 and described in Table 7-86.

Return to the Summary Table.

EEPROM Output Current Setting for CH6

Figure 7-89 EEPI6 Register
76543210
RESERVEDEEP_IOUT6
R-0hR/W-3Fh
Table 7-86 EEPI6 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT6R/W3FhOutput current setting for OUT6

7.6.1.72 EEPI7 Register (Offset = 87h) [reset = 3Fh]

EEPI7 is shown in Figure 7-90 and described in Table 7-87.

Return to the Summary Table.

EEPROM Output Current Setting for CH7

Figure 7-90 EEPI7 Register
76543210
RESERVEDEEP_IOUT7
R-0hR/W-3Fh
Table 7-87 EEPI7 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT7R/W3FhOutput current setting for OUT7

7.6.1.73 EEPI8 Register (Offset = 88h) [reset = 3Fh]

EEPI8 is shown in Figure 7-91 and described in Table 7-88.

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EEPROM Output Current Setting for CH8

Figure 7-91 EEPI8 Register
76543210
RESERVEDEEP_IOUT8
R-0hR/W-3Fh
Table 7-88 EEPI8 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT8R/W3FhOutput current setting for OUT8

7.6.1.74 EEPI9 Register (Offset = 89h) [reset = 3Fh]

EEPI9 is shown in Figure 7-92 and described in Table 7-89.

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EEPROM Output Current Setting for CH9

Figure 7-92 EEPI9 Register
76543210
RESERVEDEEP_IOUT9
R-0hR/W-3Fh
Table 7-89 EEPI9 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT9R/W3FhOutput current setting for OUT9

7.6.1.75 EEPI10 Register (Offset = 8Ah) [reset = 3Fh]

EEPI10 is shown in Figure 7-93 and described in Table 7-90.

Return to the Summary Table.

EEPROM Output Current Setting for CH10

Figure 7-93 EEPI10 Register
76543210
RESERVEDEEP_IOUT10
R-0hR/W-3Fh
Table 7-90 EEPI10 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT10R/W3FhOutput current setting for OUT10

7.6.1.76 EEPI11 Register (Offset = 8Bh) [reset = 3Fh]

EEPI11 is shown in Figure 7-94 and described in Table 7-91.

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EEPROM Output Current Setting for CH11

Figure 7-94 EEPI11 Register
76543210
RESERVEDEEP_IOUT11
R-0hR/W-3Fh
Table 7-91 EEPI11 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0hRESERVED
5-0EEP_IOUT11R/W3FhOutput current setting for OUT11

7.6.1.77 EEPP0 Register (Offset = A0h) [reset = FFh]

EEPP0 is shown in Figure 7-95 and described in Table 7-92.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH0

Figure 7-95 EEPP0 Register
76543210
EEP_PWMOUT0
R/W-FFh
Table 7-92 EEPP0 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT0R/WFFhPWM Dutycycle EEPROM Register Setting for CH0

7.6.1.78 EEPP1 Register (Offset = A1h) [reset = FFh]

EEPP1 is shown in Figure 7-96 and described in Table 7-93.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH1

Figure 7-96 EEPP1 Register
76543210
EEP_PWMOUT1
R/W-FFh
Table 7-93 EEPP1 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT1R/WFFhPWM Dutycycle EEPROM Register Setting for CH1

7.6.1.79 EEPP2 Register (Offset = A2h) [reset = FFh]

EEPP2 is shown in Figure 7-97 and described in Table 7-94.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH2

Figure 7-97 EEPP2 Register
76543210
EEP_PWMOUT2
R/W-FFh
Table 7-94 EEPP2 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT2R/WFFhPWM Dutycycle EEPROM Register Setting for CH2

7.6.1.80 EEPP3 Register (Offset = A3h) [reset = FFh]

EEPP3 is shown in Figure 7-98 and described in Table 7-95.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH3

Figure 7-98 EEPP3 Register
76543210
EEP_PWMOUT3
R/W-FFh
Table 7-95 EEPP3 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT3R/WFFhPWM Dutycycle EEPROM Register Setting for CH3

7.6.1.81 EEPP4 Register (Offset = A4h) [reset = FFh]

EEPP4 is shown in Figure 7-99 and described in Table 7-96.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH4

Figure 7-99 EEPP4 Register
76543210
EEP_PWMOUT4
R/W-FFh
Table 7-96 EEPP4 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT4R/WFFhPWM Dutycycle EEPROM Register Setting for CH4

7.6.1.82 EEPP5 Register (Offset = A5h) [reset = FFh]

EEPP5 is shown in Figure 7-100 and described in Table 7-97.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH5

Figure 7-100 EEPP5 Register
76543210
EEP_PWMOUT5
R/W-FFh
Table 7-97 EEPP5 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT5R/WFFhPWM Dutycycle EEPROM Register Setting for CH5

7.6.1.83 EEPP6 Register (Offset = A6h) [reset = FFh]

EEPP6 is shown in Figure 7-101 and described in Table 7-98.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH6

Figure 7-101 EEPP6 Register
76543210
EEP_PWMOUT6
R/W-FFh
Table 7-98 EEPP6 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT6R/WFFhPWM Dutycycle EEPROM Register Setting for CH6

7.6.1.84 EEPP7 Register (Offset = A7h) [reset = FFh]

EEPP7 is shown in Figure 7-102 and described in Table 7-99.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH7

Figure 7-102 EEPP7 Register
76543210
EEP_PWMOUT7
R/W-FFh
Table 7-99 EEPP7 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT7R/WFFhPWM Dutycycle EEPROM Register Setting for CH7

7.6.1.85 EEPP8 Register (Offset = A8h) [reset = FFh]

EEPP8 is shown in Figure 7-103 and described in Table 7-100.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH8

Figure 7-103 EEPP8 Register
76543210
EEP_PWMOUT8
R/W-FFh
Table 7-100 EEPP8 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT8R/WFFhPWM Dutycycle EEPROM Register Setting for CH8

7.6.1.86 EEPP9 Register (Offset = A9h) [reset = FFh]

EEPP9 is shown in Figure 7-104 and described in Table 7-101.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH9

Figure 7-104 EEPP9 Register
76543210
EEP_PWMOUT9
R/W-FFh
Table 7-101 EEPP9 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT9R/WFFhPWM Dutycycle EEPROM Register Setting for CH9

7.6.1.87 EEPP10 Register (Offset = AAh) [reset = FFh]

EEPP10 is shown in Figure 7-105 and described in Table 7-102.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH10

Figure 7-105 EEPP10 Register
76543210
EEP_PWMOUT10
R/W-FFh
Table 7-102 EEPP10 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT10R/WFFhPWM Dutycycle EEPROM Register Setting for CH10

7.6.1.88 EEPP11 Register (Offset = ABh) [reset = FFh]

EEPP11 is shown in Figure 7-106 and described in Table 7-103.

Return to the Summary Table.

EEPROM Output PWM Duty-cycle Setting for CH11

Figure 7-106 EEPP11 Register
76543210
EEP_PWMOUT11
R/W-FFh
Table 7-103 EEPP11 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_PWMOUT11R/WFFhPWM Dutycycle EEPROM Register Setting for CH11

7.6.1.89 EEPM0 Register (Offset = C0h) [reset = 0h]

EEPM0 is shown in Figure 7-107 and described in Table 7-104.

Return to the Summary Table.

Channel enable setting in fail-safe state 0 for channel 0 to 7.

Figure 7-107 EEPM0 Register
76543210
EEP_FS0CH7EEP_FS0CH6EEP_FS0CH5EEP_FS0CH4EEP_FS0CH3EEP_FS0CH2EEP_FS0CH1EEP_FS0CH0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-104 EEPM0 Register Field Descriptions
BitFieldTypeResetDescription
7EEP_FS0CH7R/W0hCH7 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

6EEP_FS0CH6R/W0hCH6 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

5EEP_FS0CH5R/W0hCH5 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

4EEP_FS0CH4R/W0hCH4 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

3EEP_FS0CH3R/W0hCH3 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

2EEP_FS0CH2R/W0hCH2 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

1EEP_FS0CH1R/W0hCH1 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

0EEP_FS0CH0R/W0hCH0 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

7.6.1.90 EEPM1 Register (Offset = C1h) [reset = 0h]

EEPM1 is shown in Figure 7-108 and described in Table 7-105.

Return to the Summary Table.

Channel enable setting in fail-safe state 0 for channel 8 to 11.

Figure 7-108 EEPM1 Register
76543210
RESERVEDEEP_FS0CH11EEP_FS0CH10EEP_FS0CH9EEP_FS0CH8
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-105 EEPM1 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3EEP_FS0CH11R/W0hCH11 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

2EEP_FS0CH10R/W0hCH10 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

1EEP_FS0CH9R/W0hCH9 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

0EEP_FS0CH8R/W0hCH8 setting in fail-safe state 0.

0h = Disabled

1h = Enabled

7.6.1.91 EEPM2 Register (Offset = C2h) [reset = FFh]

EEPM2 is shown in Figure 7-109 and described in Table 7-106.

Return to the Summary Table.

Channel enable setting in fail-safe state 1 for channel 0 to 7.

Figure 7-109 EEPM2 Register
76543210
EEP_FS1CH7EEP_FS1CH6EEP_FS1CH5EEP_FS1CH4EEP_FS1CH3EEP_FS1CH2EEP_FS1CH1EEP_FS1CH0
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 7-106 EEPM2 Register Field Descriptions
BitFieldTypeResetDescription
7EEP_FS1CH7R/W1hCH7 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

6EEP_FS1CH6R/W1hCH6 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

5EEP_FS1CH5R/W1hCH5 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

4EEP_FS1CH4R/W1hCH4 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

3EEP_FS1CH3R/W1hCH3 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

2EEP_FS1CH2R/W1hCH2 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

1EEP_FS1CH1R/W1hCH1 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

0EEP_FS1CH0R/W1hCH0 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

7.6.1.92 EEPM3 Register (Offset = C3h) [reset = Fh]

EEPM3 is shown in Figure 7-110 and described in Table 7-107.

Return to the Summary Table.

Channel enable setting in fail-safe state 1 for channel 8 to 11.

Figure 7-110 EEPM3 Register
76543210
RESERVEDEEP_FS1CH11EEP_FS1CH10EEP_FS1CH9EEP_FS1CH8
R-0hR/W-1hR/W-1hR/W-1hR/W-1h
Table 7-107 EEPM3 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3EEP_FS1CH11R/W1hCH11 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

2EEP_FS1CH10R/W1hCH10 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

1EEP_FS1CH9R/W1hCH9 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

0EEP_FS1CH8R/W1hCH8 setting in fail-safe state 1.

0h = Disabled

1h = Enabled

7.6.1.93 EEPM4 Register (Offset = C4h) [reset = FFh]

EEPM4 is shown in Figure 7-111 and described in Table 7-108.

Return to the Summary Table.

Figure 7-111 EEPM4 Register
76543210
EEP_DIAGENCH7EEP_DIAGENCH6EEP_DIAGENCH5EEP_DIAGENCH4EEP_DIAGENCH3EEP_DIAGENCH2EEP_DIAGENCH1EEP_DIAGENCH0
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 7-108 EEPM4 Register Field Descriptions
BitFieldTypeResetDescription
7EEP_DIAGENCH7R/W1hChannel 7 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

6EEP_DIAGENCH6R/W1hChannel 6 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

5EEP_DIAGENCH5R/W1hChannel 5 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

4EEP_DIAGENCH4R/W1hChannel 4 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

3EEP_DIAGENCH3R/W1hChannel 3 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

2EEP_DIAGENCH2R/W1hChannel 2 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

1EEP_DIAGENCH1R/W1hChannel 1 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

0EEP_DIAGENCH0R/W1hChannel 0 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

7.6.1.94 EEPM5 Register (Offset = C5h) [reset = Fh]

EEPM5 is shown in Figure 7-112 and described in Table 7-109.

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Figure 7-112 EEPM5 Register
76543210
RESERVEDEEP_DIAGENCH11EEP_DIAGENCH10EEP_DIAGENCH9EEP_DIAGENCH8
R-0hR/W-1hR/W-1hR/W-1hR/W-1h
Table 7-109 EEPM5 Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0hRESERVED
3EEP_DIAGENCH11R/W1hChannel 11 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

2EEP_DIAGENCH10R/W1hChannel 10 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

1EEP_DIAGENCH9R/W1hChannel 9 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

0EEP_DIAGENCH8R/W1hChannel 8 diagnostics enable EEPROM register.

0h = Disabled

1h = Enabled

7.6.1.95 EEPM6 Register (Offset = C6h) [reset = 0h]

EEPM6 is shown in Figure 7-113 and described in Table 7-110.

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Figure 7-113 EEPM6 Register
76543210
RESERVEDEEP_LDORESERVEDEEP_EXPENEEP_DEVADDR
R-0hR/W-0hR-0hR/W-0hR/W-0h
Table 7-110 EEPM6 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0hRESERVED
6EEP_LDOR/W0hLDO output voltage setting.

0h = 5.0 V

1h = 4.4 V

5RESERVEDR0hRESERVED
4EEP_EXPENR/W0hPWM generator exponetinal dimmng enable register.

0h = Disabled

1h = Enabled

3-0EEP_DEVADDRR/W0hDevice slave address EEPROM register

0h = slave address is 0000b

1h = slave address is 0001b

2h = slave address is 0010b

3h = slave address is 0011b

4h = slave address is 0100b

5h = slave address is 0101b

6h = slave address is 0110b

7h = slave address is 0111b

8h = slave address is 1000b

9h = slave address is 1001b

Ah = slave address is 1010b

Bh = slave address is 1011b

Ch = slave address is 1100b

Dh = slave address is 1101b

Eh = slave address is 1110b

Fh = slave address is 1111b

Reset value is 8h for TPS929120A version

7.6.1.96 EEPM7 Register (Offset = C7h) [reset = A7h]

EEPM7 is shown in Figure 7-114 and described in Table 7-111.

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Figure 7-114 EEPM7 Register
76543210
EEP_PWMFREQEEP_INTADDREEP_OFAFEEP_REFRANGE
R/W-AhR/W-0hR/W-1hR/W-3h
Table 7-111 EEPM7 Register Field Descriptions
BitFieldTypeResetDescription
7-4EEP_PWMFREQR/WAhPWM frequency selection EEPROM register

0h = 200 Hz

1h = 250 Hz

2h = 300 Hz

3h = 350 Hz

4h = 400 Hz

5h = 500 Hz

6h = 600 Hz

7h = 800 Hz

8h = 1000 Hz

9h = 1200 Hz

Ah = 2 kHz

Bh = 4 kHz

Ch = 5.9 kHz

Dh = 7.8 kHz

Eh = 9.6 kHz

Fh = 20.8 kHz

3EEP_INTADDRR/W0hSlave address selection bit.
0x0: Deivce slave address set by ADDR2/ADDR1/ADDR0 pins configuration
0x1: Device slave address set by EEP_DEVADDR EEPROM register
2EEP_OFAFR/W1hOutput failure state setting.
0x0: One-fails-others-on.
0x1: One-fails-all-fail.
1-0EEP_REFRANGER/W3hReference current ratio setting EEPROM register

0h = 64

1h = 128

2h = 256

3h = 512

7.6.1.97 EEPM8 Register (Offset = C8h) [reset = 3h]

EEPM8 is shown in Figure 7-115 and described in Table 7-112.

Return to the Summary Table.

Figure 7-115 EEPM8 Register
76543210
RESERVEDEEP_FLTIMEOUTEEP_ADCLOWSUPTH
R-0hR/W-0hR/W-3h
Table 7-112 EEPM8 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0hREVSERVED
6-4EEP_FLTIMEOUTR/W0hFlexWire timeout timer setting EEPROM register.

0h = 1 ms

1h = 125 µs

2h = 250 µs

3h = 500 µs

4h = 1.25 ms

5h = 2.5 ms

6h = 5 ms

7h = 10 ms

3-0EEP_ADCLOWSUPTHR/W3hADC Supply monitor threshold setting EEPROM register.

0h = 5 V

1h = 6 V

2h = 7 V

3h = 8 V

4h = 9 V

5h = 10 V

6h = 11 V

7h = 12 V

8h = 13 V

9h = 14 V

Ah = 15 V

Bh = 16 V

Ch = 17 V

Dh = 18 V

Eh = 19 V

Fh = 20 V

7.6.1.98 EEPM9 Register (Offset = C9h) [reset = 0h]

EEPM9 is shown in Figure 7-116 and described in Table 7-113.

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Figure 7-116 EEPM9 Register
76543210
EEP_ODIOUTEEP_ODPW
R/W-0hR/W-0h
Table 7-113 EEPM9 Register Field Descriptions
BitFieldTypeResetDescription
7-4EEP_ODIOUTR/W0hOn-demand diagnostics output current setting EEPROM register.
0x0 to 0xE: IOUT = (CONF_ODIOUT*4+1)/64*I(FULL_RANGE)
0xF: ODIOUT is using its channel setting current
3-0EEP_ODPWR/W0hOn-demand diagnostics pulse-width setting EEPROM register.

0h = 100 µs

1h = 20 µs

2h = 30 µs

3h = 50 µs

4h = 80 µs

5h = 150 µs

6h = 200 µs

7h = 300 µs

8h = 500 µs

9h = 800 µs

Ah = 1 ms

Bh = 1.2 ms

Ch = 1.5 ms

Dh = 2 ms

Eh = 3 ms

Fh = 5 ms

7.6.1.99 EEPM10 Register (Offset = CAh) [reset = 0h]

EEPM10 is shown in Figure 7-117 and described in Table 7-114.

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Figure 7-117 EEPM10 Register
76543210
EEP_WDTIMEREEP_INITTIMER
R/W-0hR/W-0h
Table 7-114 EEPM10 Register Field Descriptions
BitFieldTypeResetDescription
7-4EEP_WDTIMERR/W0hWatchdog timer setting EEPROM register.

0h = Disabled, do not automatically enter fail-safe state

1h = 200 µs

2h = 500 µs

3h = 1 ms

4h = 2 ms

5h = 5 ms

6h = 10 ms

7h = 20 ms

8h = 50 ms

9h = 100 ms

Ah = 200 ms

Bh = 500 ms

Ch = 0 µs; direct enter fail-safe state

Dh = 0 µs; direct enter fail-safe state

Eh = 0 µs; direct enter fail-safe state

Fh = 0 µs; direct enter fail-safe state

3-0EEP_INITTIMERR/W0hInitialization timer setting EEPROM register.

0h = 0 ms

1h = 50 ms

2h = 20 ms

3h = 10 ms

4h = 5 ms

5h = 2 ms

6h = 1 ms

7h = 500 µs

8h = 200 µs

9h = 100 µs

Ah = 50 µs

Bh = 50 µs

Ch = 50 µs

Dh = 50 µs

Eh = 50 µs

Fh = 50 µs

7.6.1.100 EEPM11 Register (Offset = CBh) [reset = 0h]

EEPM11 is shown in Figure 7-118 and described in Table 7-115.

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Figure 7-118 EEPM11 Register
76543210
EEP_ADCSHORTTH
R/W-0h
Table 7-115 EEPM11 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_ADCSHORTTHR/W0hADC short detection threshold setting EEPROM register

7.6.1.101 EEPM15 Register (Offset = CFh) [reset = 23h]

EEPM15 is shown in Figure 7-119 and described in Table 7-116.

Return to the Summary Table.

Figure 7-119 EEPM15 Register
76543210
EEP_CRC
R/W-B3h
Table 7-116 EEPM15 Register Field Descriptions
BitFieldTypeResetDescription
7-0EEP_CRCR/WB3hCRC reference for all EEPROM register, manufacture default CRC code is B3h for TPS929120 and 09h for TPS929120A version.