JAJSHX9D september   2019  – january 2021 UCC12050

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーションと実装
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 UVLO, Power-Up, and Power-Down Behavior
      3. 7.3.3 VISO Load Recommended Operating Area
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 External Clocking and Synchronization
      6. 7.3.6 VISO Output Voltage Selection
      7. 7.3.7 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VISO Output Capacitor Selection
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical and Packaging Information

8.2.2.1 VISO Output Capacitor Selection

The UCC12050 is optimized to run with an effective output capacitance of 5 µF to 20 µF. A ceramic capacitor is recommended. Ceramic capacitors have DC-Bias and temperature derating effects, which both have influence the final effective capacitance. Choose the right capacitor carefully in combination with considering its package size, dielectric and voltage rating. It is good design practice to include one 0.1-µF capacitor close to the device for high-frequency noise reduction.