JAJSJ67E may 2020 – july 2023 UCC28782
PRODUCTION DATA
The UCC28782 provides extensive protections on different system fault scenarios. The protection features are summarized in Table 8-3.
The system fault responses of UCC28782A and UCC28782AD are all auto-recovery.
The fault responses of UCC28782BDL are latch-off for OVP, OPP, PPL, OCP, SCP, OTP on the FLT pin, and OTP on the CS pin. The remaining faults are auto-recovery.
The fault responses of UCC28782CD are latch-off for OVP and OTP on the FLT pin. The remaining faults are auto-recovery.
The response for any latch-off fault will disable the switching until a latch-reset event is detected. Resetting a latched fault can be achieved by either discharging VVDD < VVDD(RST) or triggering the LZC detection on the XCD pin. Due to the large input bulk capacitor, VVDD can stay above VVDD(RST) for a long time at no output load after the AC line is removed. If there is a need to reset the fault condition quickly for fast recovery of the output voltage, the application circuit for the XCD pin can be used. The detection timing of the XCD pin allows the latch to be reset and initiate the switching attempt, after reapplying the AC line in less than 2 seconds.
PROTECTION | SENSING | THRESHOLD | DELAY TO ACTION | ACTION BY UCC28782A, UCC28782AD | ACTION BY UCC28782BDL | ACTION BY UCC28782CD |
---|---|---|---|---|---|---|
VDD UVLO | VDD voltage | VVDD(OFF) ≤ VVDD ≤ VVDD(ON) | None | UVLO reset | UVLO reset | UVLO reset |
Brown-in detection | VS current | IVSL ≤ IVSL(RUN) | 4 PWML pulses | UVLO reset | UVLO reset | UVLO reset |
Brown-out detection | VS current | IVSL ≤ IVSL(STOP) | tBO (60ms) plus 3 confirming PWML pulses | UVLO reset | UVLO reset | UVLO reset |
Over-power protection (OPP) | CS voltage | VCST(OPP) ≤ VCST ≤ VCST(MAX) | tOPP (160 ms) | tFDR restart (1.5s) | Latch off | tFDR restart |
Peak-power limit (PPL) | CS voltage | VCST ≤ VCST(MAX) | ||||
Over-current protection (OCP) | CS voltage | VCS ≥ VOCP | 3 PWML pulses | tFDR restart | Latch off | tFDR restart |
Output short-circuit protection (SCP) | CS, VS, and VDD voltages | (1) VVDD = VVDD(OFF) & VCST ≥ VCST(OPP) ; (2) VVDD = VVDD(OFF) & VVS ≤ VVS(SM2) | ≤ tOPP | tFDR restart | Latch off | tFDR restart |
Output over-voltage protection (OVP) | VS voltage | VVS ≥ VOVP | 3 PWML pulses | tFDR restart | Latch off | Latch off |
Over-temperature protection on FLT pin (OTP) | FLT voltage | RNTC ≤ RNTCTH | tFLT(NTC) (50 µs) | UVLO reset until RNTC ≥ RNTCR | Latch off | Latch off |
Over-temperature protection on CS pin (OTP) | CS voltage | VCS ≥ VOCP | 2 PWMH pulses | tFDR restart | Latch off | tFDR restart |
Input over-voltage protection (IOVP) | FLT voltage | VFLT ≥ VIOVPTH | tFLT(IOVP) (750 µs) | UVLO reset until VFLT < VIOVPTH - VIOVPR | UVLO reset until VFLT < VIOVPTH - VIOVPR | UVLO reset until VFLT < VIOVPTH - VIOVPR |
Thermal shutdown | Junction temperature | TJ ≥ TJ(STOP) | 3 PWML pulses | UVLO reset | UVLO reset | UVLO reset |