JAJSJM2B July   2022  – April 2024 TPS929240-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Bias and Power
        1. 6.3.1.1 Power Bias (VBAT)
        2. 6.3.1.2 5V Low-Drop-Out Linear Regulator (VLDO)
        3. 6.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 6.3.1.4 Power Supply (SUPPLY)
        5. 6.3.1.5 Programmable Low Supply Warning
      2. 6.3.2 Constant Current Output
        1. 6.3.2.1 Reference Current with External Resistor (REF)
        2. 6.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 6.3.3 PWM Dimming
        1. 6.3.3.1 PWM Generator
        2. 6.3.3.2 PWM Dimming Frequency
        3. 6.3.3.3 Blank Time
        4. 6.3.3.4 Phase Shift PWM Dimming
        5. 6.3.3.5 Linear Brightness Control
        6. 6.3.3.6 Exponential Brightness Control
      4. 6.3.4 FAIL-SAFE State Operation
      5. 6.3.5 On-Chip, 8-Bit, Analog-to-Digital Converter (ADC)
        1. 6.3.5.1 Minimum On Time for ADC Measurement
        2. 6.3.5.2 ADC Auto Scan
        3. 6.3.5.3 ADC Error
      6. 6.3.6 Diagnostic and Protection in NORMAL State
        1. 6.3.6.1  VBAT Undervoltage Lockout Diagnostics in NORMAL state
        2. 6.3.6.2  Low-Supply Warning Diagnostics in NORMAL State
        3. 6.3.6.3  Supply Undervoltage Diagnostics in NORMAL State
        4. 6.3.6.4  Reference Diagnostics in NORMAL state
        5. 6.3.6.5  Pre-Thermal Warning in NORMAL state
        6. 6.3.6.6  Overtemperature Protection in NORMAL state
        7. 6.3.6.7  Overtemperature Shutdown in NORMAL state
        8. 6.3.6.8  LED Open-Circuit Diagnostics in NORMAL state
        9. 6.3.6.9  LED Short-Circuit Diagnostics in NORMAL state
        10. 6.3.6.10 Single-LED Short-Circuit Detection in NORMAL state
        11. 6.3.6.11 EEPROM CRC Error in NORMAL state
        12. 6.3.6.12 Communication Loss Diagnostic in NORMAL State
        13. 6.3.6.13 Fault Masking in NORMAL state
        14.       53
      7. 6.3.7 Diagnostic and Protection in FAIL-SAFE states
        1. 6.3.7.1  Supply Undervoltage Lockout Diagnostics in FAIL-SAFE states
        2. 6.3.7.2  Low-Supply Warning Diagnostics in FAIL-SAFE states
        3. 6.3.7.3  Supply Undervoltage Diagnostics in FAIL-SAFE State
        4. 6.3.7.4  Reference Diagnostics in FAIL-SAFE states
        5. 6.3.7.5  Pre-Thermal Warning in FAIL-SAFE state
        6. 6.3.7.6  Overtemperature Protection in FAIL-SAFE state
        7. 6.3.7.7  Overtemperature Shutdown in FAIL-SAFE state
        8. 6.3.7.8  LED Open-Circuit Diagnostics in FAIL-SAFE state
        9. 6.3.7.9  LED Short-Circuit Diagnostics in FAIL-SAFE state
        10. 6.3.7.10 Single-LED Short-Circuit Detection in FAIL-SAFE state
        11. 6.3.7.11 EEPROM CRC Error in FAIL-SAFE State
        12. 6.3.7.12 Fault Masking in FAIL-SAFE state
        13.       Diagnostics Table in FAIL-SAFE State
      8. 6.3.8 OFAF Setup In FAIL-SAFE state
      9. 6.3.9 ERR Output
    4. 6.4 Device Functional Modes
      1. 6.4.1 POR State
      2. 6.4.2 INITIALIZATION state
      3. 6.4.3 NORMAL state
      4. 6.4.4 FAIL-SAFE state
      5. 6.4.5 PROGRAM state
    5. 6.5 Programming
      1. 6.5.1 FlexWire Protocol
        1. 6.5.1.1 Protocol Overview
        2. 6.5.1.2 UART Interface Address Setting
        3. 6.5.1.3 Status Response
        4. 6.5.1.4 Synchronization Byte
        5. 6.5.1.5 Device Address Byte
        6. 6.5.1.6 Register Address Byte
        7. 6.5.1.7 Data Frame
        8. 6.5.1.8 CRC Frame
        9. 6.5.1.9 Burst Mode
      2. 6.5.2 Registers Lock
      3. 6.5.3 Register Default Data
      4. 6.5.4 EEPROM Programming
        1. 6.5.4.1 Chip Selection by Pulling REF Pin High
        2. 6.5.4.2 Chip Selection by ADDR Pins Configuration
        3. 6.5.4.3 EEPROM Register Access and Burn
        4. 6.5.4.4 EEPROM PROGRAM State Exit
    6. 6.6 Register Maps
      1. 6.6.1 BRT Registers
      2. 6.6.2 IOUT Registers
      3. 6.6.3 CONF Registers
      4. 6.6.4 CTRL Registers
      5. 6.6.5 FLAG Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Smart Rear Lamp with Distributed LED Drivers
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.6.4 CTRL Registers

Table 6-126 lists the memory-mapped registers for the CTRL registers. All register offset addresses not listed in Table 6-126 should be considered as reserved locations and the register contents should not be modified.

Control Register

Table 6-126 CTRL Registers
OffsetAcronymRegister NameSection
90hADCCHADC Channel Selection SettingGo
91hCLRControl Register for ClearGo
92hDEBUGControl Register for DebugGo
93hLOCKControl Register for Register LockGo
94hCLRREGControl Register for Clear RegisterGo
95hCTRL-RReserved RegisterGo
96hCTRLGATEGate Register for MISC and LOCKGo
97hEEPControl Register for EEP OperationGo
98hEEPGATEGate Register for EEPGo

Complex bit access types are encoded to fit into small table cells. Table 6-127 shows the codes that are used for access types in this section.

Table 6-127 CTRL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.6.4.1 ADCCH Register (Offset = 90h) [Reset = 00h]

ADCCH is shown in Figure 6-120 and described in Table 6-128.

Return to the Summary Table.

Figure 6-120 ADCCH Register
76543210
RESERVEDADCCHSEL
R-0hR/W-0h
Table 6-128 ADCCH Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h Reserved
4-0ADCCHSELR/W0h Channel selection setting for ADC voltage measurement, write this register automatically initiates the ADC conversion

6.6.4.2 CLR Register (Offset = 91h) [Reset = 00h]

CLR is shown in Figure 6-121 and described in Table 6-129.

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Figure 6-121 CLR Register
76543210
RESERVEDCLRFSCLRFAULTCLRPOR
R-0hR/W-0hR/W-0hR/W-0h
Table 6-129 CLR Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0h Reserved
2CLRFSR/W0h Write 1 to force device to exit fail-safe state to normal state, automatically returns to 0
1CLRFAULTR/W0h Write 1 to clear all fault flags, automatically returns to 0
0CLRPORR/W0h Write 1 to clear POR fault flag, automatically returns to 0

6.6.4.3 DEBUG Register (Offset = 92h) [Reset = 00h]

DEBUG is shown in Figure 6-122 and described in Table 6-130.

Return to the Summary Table.

Figure 6-122 DEBUG Register
76543210
RESERVEDFORCEFSFPRCEERR
R-0hR/W-0hR/W-0h
Table 6-130 DEBUG Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0h Reserved
1FORCEFSR/W0h Write 1 to force device to fail-safe state, automatically returns to 0
0FPRCEERRR/W0h Write 1 to set FLAG_ERR to 1 and ERR output pulled down for 50µs in normal state, automatically returns to 0

6.6.4.4 LOCK Register (Offset = 93h) [Reset = 03h]

LOCK is shown in Figure 6-123 and described in Table 6-131.

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Figure 6-123 LOCK Register
76543210
RESERVEDBRTLOCKCONFLOCKIOUTLOCK
R-0hR/W-0hR/W-1hR/W-1h
Table 6-131 LOCK Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0h Reserved
2BRTLOCKR/W0h BRT register lock
0h = Write protection is disabled
1h = Write protection is enabled
1CONFLOCKR/W1h CONF register lock
0h = Write protection is disabled
1h = Write protection is enabled
0IOUTLOCKR/W1h IOUT register lock
0h = Write protection is disabled
1h = Write protection is enabled

6.6.4.5 CLRREG Register (Offset = 94h) [Reset = 00h]

CLRREG is shown in Figure 6-124 and described in Table 6-132.

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Figure 6-124 CLRREG Register
76543210
RESERVEDSOFTRESETEEPLOADREGDEFAULT
R-0hR/W-0hR/W-0hR/W-0h
Table 6-132 CLRREG Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR0h Reserved
2SOFTRESETR/W0h Write 1 to reset all state machine and all registers, automatically returns to 0
1EEPLOADR/W0h Write 1 to load EEP data to corresponding registers, automatically returns to 0
0REGDEFAULTR/W0h Write 1 to set all registers to default value, automatically returns to 0

6.6.4.6 CTRL-R Register (Offset = 95h) [Reset = 00h]

CTRL-R is shown in Figure 6-125 and described in Table 6-133.

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Figure 6-125 CTRL-R Register
76543210
RESERVED
R-0h
Table 6-133 CTRL-R Register Field Descriptions
BitFieldTypeResetDescription
7-0RESERVEDR0h Reserved

6.6.4.7 CTRLGATE Register (Offset = 96h) [Reset = 00h]

CTRLGATE is shown in Figure 6-126 and described in Table 6-134.

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Figure 6-126 CTRLGATE Register
76543210
CTRLGATE
R/W-0h
Table 6-134 CTRLGATE Register Field Descriptions
BitFieldTypeResetDescription
7-0CTRLGATER/W0h Gate register for DEBUG, LOCK and CLRREG registers access, write 43h, 4Fh, 44h and 45h one-byte by one-byte

6.6.4.8 EEP Register (Offset = 97h) [Reset = 00h]

EEP is shown in Figure 6-127 and described in Table 6-135.

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Figure 6-127 EEP Register
76543210
RESERVEDEEPPROGEEPMODE
R-0hR/W-0hR/W-0h
Table 6-135 EEP Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0h Reserved
1EEPPROGR/W0h EEPROM burning starts in EEPROM programming state only, automatically returns to 0
0EEPMODER/W0h EEPROM programming state setting
0h = Disabled
1h = Enabled

6.6.4.9 EEPGATE Register (Offset = 98h) [Reset = 00h]

EEPGATE is shown in Figure 6-128 and described in Table 6-136.

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Figure 6-128 EEPGATE Register
76543210
EEPGATE
R/W-0h
Table 6-136 EEPGATE Register Field Descriptions
BitFieldTypeResetDescription
7-0EEPGATER/W0h Gate register for EEP registers access, write 00h, 04h, 02h, 09h, 02h and 09h one-byte by one-byte