JAJSKN2B November   2020  – September 2021 TPS25864-Q1 , TPS25865-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Power-Down or Undervoltage Lockout
      2. 10.3.2  Input Overvoltage Protection (OVP) - Continuously Monitored
      3. 10.3.3  Buck Converter
      4. 10.3.4  FREQ/SYNC
      5. 10.3.5  Bootstrap Voltage (BOOT)
      6. 10.3.6  Minimum ON-Time, Minimum OFF-Time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Selectable Output Voltage (VSET)
      9. 10.3.9  Current Limit and Short Circuit Protection
        1. 10.3.9.1 USB Switch Current Limit
        2. 10.3.9.2 Interlocking for Two-Level USB Switch Current Limit
        3. 10.3.9.3 Cycle-by-Cycle Buck Current Limit
        4. 10.3.9.4 OUT Current Limit
      10. 10.3.10 Cable Compensation
      11. 10.3.11 Thermal Management With Temperature Sensing (TS) and OTSD
      12. 10.3.12 Thermal Shutdown
      13. 10.3.13 USB Specification Overview
      14. 10.3.14 USB Port Operating Modes
        1. 10.3.14.1 Dedicated Charging Port (DCP) Mode
          1. 10.3.14.1.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.3.14.1.2 DCP Divider-Charging Scheme
          3. 10.3.14.1.3 DCP 1.2-V Charging Scheme
        2. 10.3.14.2 DCP Auto Mode
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Output Voltage Setting
        2. 11.2.2.2 Switching Frequency
        3. 11.2.2.3 Inductor Selection
        4. 11.2.2.4 Output Capacitor Selection
        5. 11.2.2.5 Input Capacitor Selection
        6. 11.2.2.6 Bootstrap Capacitor Selection
        7. 11.2.2.7 Undervoltage Lockout Set-Point
        8. 11.2.2.8 Cable Compensation Set-Point
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Ground Plane and Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

10.3.1 Power-Down or Undervoltage Lockout

The device is in low power mode if the IN terminal voltage is less than VUVLO, so the part is considered dead and all the terminals are high impedance. Once the IN voltage rises above the VUVLO threshold, the IC enters sleep mode or active mode, depending on the EN/UVLO voltage.

The voltage on the EN/UVLO pin controls the ON/OFF operation of the TPS2586x-Q1. An EN/UVLO pin voltage higher than VEN/UVLO-H is required to start the internal regulator. The internal USB monitoring circuitry is on when VIN is within the operation range and the EN/UVLO threshold is cleared.

The EN/UVLO pin is an input and cannot be left open or floating. The simplest way to enable the operation of the TPS2586x-Q1 is to connect EN to SENSE. This connection allows self-startup of the TPS2586x-Q1 when VIN is within the operation range. Note that you cannot connect the EN to IN pin directly for self-startup.

Many applications benefit from the employment of enable dividers RENT and RENB to establish a precision system UVLO level for the TPS2586x-Q1 shown in Figure 10-1. The system UVLO can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. To ensure the USB port VBUS is within the 5-V operating range as required for USB compliance (for the latest USB specifications and requirements, refer to USB.org), TI suggests that the RENT and RENB resistors be chosen such that the TPS2586x-Q1 enables when VIN is approximately 6 V. Considering the dropout voltage of the buck regulator and IR losses in the system, 6 V provides adequate margin to maintain VBUS within USB specifications. If system requirements, such as a warm crank (start) automotive scenario, require operation with VIN < 6 V, the values of RENT and RENB can be calculated assuming a lower VIN. An external logic signal can also be used to drive the EN/UVLO input when a microcontroller is present and it is desirable to enable or disable the USB port remotely for other reasons.

GUID-59C446F7-F51F-47A3-98A2-15364B61CA23-low.gifFigure 10-1 System UVLO by Enable Divider

UVLO configuration using external resistors is governed by the following equations:

Equation 1. GUID-FC41B6FE-DBEA-47D4-92E7-7D8A8C3A1458-low.gif
Equation 2. GUID-660CA966-89C7-4E4C-889E-3DB32EF8309C-low.gif

For example:

VIN(ON) = 6 V

RENT = 20 kΩ

Equation 3. RENB = [(VEN-VOUT-H) / (VIN(ON) – VEN)] × RENT

RENB = 5 kΩ

Therefore, VIN(OFF) = 5.5 V