JAJSMF6C november   2021  – april 2023 TPS2597

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 8.3.2 Overvoltage Lockout (OVLO)
      3. 8.3.3 Overvoltage Clamp (OVC)
      4. 8.3.4 Inrush Current, Overcurrent, and Short Circuit Protection
        1. 8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
        2. 8.3.4.2 Circuit-Breaker
        3. 8.3.4.3 Active Current Limiting
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5 Analog Load Current Monitor
      6. 8.3.6 Overtemperature Protection (OTP)
      7. 8.3.7 Fault Response and Indication (FLT)
      8. 8.3.8 Power-Good Indication (PG)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Self-Controlled
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting Undervoltage and Overvoltage Thresholds
        3. 9.2.2.3 Setting Output Voltage Rise Time (tR)
        4. 9.2.2.4 Setting Power-Good Assertion Threshold
        5. 9.2.2.5 Setting Overcurrent Threshold (ILIM)
        6. 9.2.2.6 Setting Overcurrent Blanking Interval (tITIMER)
      3. 9.2.3 Application Curves
    3. 9.3 Parallel Operation
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output Short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

9.2.2.3 Setting Output Voltage Rise Time (tR)

For a successful design, the junction temperature of the device must be kept below the absolute maximum rating during both dynamic (start-up) and steady-state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and inrush current limit required with system capacitance to avoid thermal shutdown during start-up.

The slew rate (SR) needed to achieve the desired output rise time can be calculated as:

Equation 12. S R   (V/ms) = V IN   ( V ) t R   ( m s ) = 12   V 20   m s = 0.6   V / m s

The CdVdt needed to achieve this slew rate can be calculated as:

Equation 13. C dVdt   p F = 3300 S R   V / m s = 3300 0.6 = 5500   p F

Choose the nearest standard capacitor value as 5600 pF.

For this slew rate, the inrush current can be calculated as:

Equation 14. I INRUSH   m A = S R   (V/ms) ×  C OUT   µ F = 0.6   ×   470 = 282   m A  

The average power dissipation inside the part during inrush can be calculated as:

Equation 15. P D INRUSH   W = I INRUSH   A   ×   V IN   V 2 = 0.282   ×   12 2 = 1.69   W
For the given power dissipation, the thermal shutdown time of the device must be greater than the ramp-up time tR to avoid start-up failure. Figure 9-3 shows the thermal shutdown limit. For 1.69 W of power, the shutdown time is more than 10 s, which is very large as compared to tR = 20 ms. Therefore, it is safe to use 20 ms as the start-up time for this application.
GUID-20211108-SS0I-RVGJ-ZSJP-23TJZPKCZLZS-low.svg Figure 9-3 Thermal Shut-Down Plot During Inrush
Note: In some systems, there can be active load circuits (for example, DC-DC converters) with low turn-on threshold voltages which can start drawing power before the eFuse has completed the inrush sequence. This action can cause additional power dissipation inside the eFuse during start-up and can lead to thermal shutdown. TI recommends to use the Power Good (PG) pin of the eFuse to enable and disable the load circuit. This action ensures that the load is turned on only when the eFuse has completed its start-up and is ready to deliver full power without the risk of hitting thermal shutdown.