JAJSNH8C December   2022  – August 2024 TLV2365 , TLV365

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Rail-to-Rail Input
      2. 7.3.2 Input and ESD Protection
      3. 7.3.3 Driving Capacitive Loads
      4. 7.3.4 Active Filter
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Overdrive Recovery Performance
      2. 8.1.2 Achieving an Output Level of Zero Volts
    2. 8.2 Typical Applications
      1. 8.2.1 Second-Order Low-Pass Filter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 ADC Driver and Reference Buffer
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™シミュレーション ソフトウェア (無償ダウンロード)
        3. 9.1.1.3 DIP アダプタ評価基板
        4. 9.1.1.4 DIYAMP-EVM
        5. 9.1.1.5 TI のリファレンス・デザイン
        6. 9.1.1.6 Analog Filter Designer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

TLV365 TLV2365 TLV365 DBV Package, 5-Pin SOT-23 (Top View) Figure 5-1 TLV365 DBV Package, 5-Pin SOT-23 (Top View)
Table 5-1 Pin Functions: TLV365
PIN TYPE DESCRIPTION
NAME NO.
–IN 4 Input Negative (inverting) input signal
+IN 3 Input Positive (noninverting) input signal
V– 2 — Negative (lowest) power supply
V+ 5 — Positive (highest) power supply
VOUT 1 Output Output
Figure 5-2 TLV2365 D Package, 8-Pin SOIC and DGK Package, 8-Pin VSSOP (Top View)
Table 5-2 Pin Functions: TLV2365
PIN TYPE DESCRIPTION
NAME NO.
–IN A 2 Input Negative (inverting) input signal, channel A
–IN B 6 Input Negative (inverting) input signal, channel B
+IN A 3 Input Positive (noninverting) input signal, channel A
+IN B 5 Input Positive (noninverting) input signal, channel B
V– 4 — Negative (lowest) power supply
V+ 8 — Positive (highest) power supply
VOUTA 1 Output Output, channel A
VOUTB 7 Output Output, channel B