JAJSVL9 November   2024 UCC33421-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Safety-Related Certifications
    7. 6.7 Electrical Characteristics
    8. 6.8 External BOM Components
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Disable
      2. 7.3.2 Output Voltage Soft-Start
      3. 7.3.3 Output Voltage Steady-State Regulation
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Input Under-voltage and Over-Voltage Lockout
        2. 7.3.4.2 Output Under-Voltage Protection
        3. 7.3.4.3 Output Over-Voltage Protection
        4. 7.3.4.4 Over-Temperature Protection
        5. 7.3.4.5 Fault Reporting and Auto-Restart
      5. 7.3.5 VCC Load Recommended Operating Area
      6. 7.3.6 Electromagnetic Compatibility (EMC) Considerations
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical and Packaging Information

5 Pin Configuration and Functions

UCC33421-Q1 DHA SOIC 16-pin Package (Top View) Figure 5-1 DHA SOIC 16-pin Package (Top View)
Table 5-1 Pin Functions
PIN TYPE (1) DESCRIPTION
NAME NO.
EN/FLT 1 I/O

Multi-function Enable input pin and fault output pin. Connect to microcontroller through an 18kΩ or greater pull-up resistor.

Enable input pin: Forcing EN low disables the device. Pull high to enable normal device functionality.

Fault output pin: This pin is pulled low for 200μs to alert that power converter is shutdown due to fault condition
VINP 2 P Primary side input supply voltage pin. 15nF (CIN1) and 10μF (CIN2) ceramic bypass capacitors placed close to device pins are required between VINP and GNDP pins
3
GNDP 4 G Power ground return connection for VINP.
5
6
7
8
SEL 9 I VCC selection pin. VCC setpoint is 5.0V when SEL is connected to VCC, and 5.5V when SEL is shorted to GNDS
VCC 10 P Isolated supply output voltage pin. 15nF (COUT1) and 22μF (COUT2) ceramic bypass capacitors placed close to device pins are required between VCC and GNDS pins
11
GNDS 12 G Power ground return connection for VCC.
13
14
15
16
(1) P = Power, G = Ground, I = Input, O = Output