JAJSVU5 December   2024 UCC57102Z-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Driver Stage
      3. 6.3.3 Desaturation (DESAT) Protection
      4. 6.3.4 Fault (FLT)
      5. 6.3.5 VREF
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Undervoltage Lockout
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.6 Switching Characteristics

VDD = 15 V, VEE = 0 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VEE to GND, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted. (1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tRA, tRBOutput Rise TimeCL=1.8nF, 10% to 90%, Vin = 0 to 3.3V818ns
tFA, tFBOutput Fall TimeCL=1.8nF, 90% to 10%, Vin = 0 to 3.3V1432ns
tD2Propagation Delay – Input falling to output fallingCL=1.8nF, from 1V falling on Vin to 90% of output fall, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle2850ns
tD1Propagation Delay – Input rising to output risingCL=1.8nF, from 2V rising on Vin to 10% of output rise, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle2650ns
tPWminMinimum Input Pulse Width That Passes to OutputCL=1.8nF, Vin=0 - 3.3V, Fsw=500kHz, Vo >2V915ns
tPWDPulse Width DistortionInput Pulse Width = 100ns,  500kHz
tD2 – tD1,CL=1.8nF		-1010ns
(1) Switching parameters are not tested in production.