JAJU850 May   2022 TPSI3050 , TPSI3050-Q1 , TPSI3052 , TPSI3052-Q1

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 System Design Theory
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
    3. 2.3 Design Considerations
      1. 2.3.1 TPSI3050-Q1
      2. 2.3.2 AMC23C10
      3. 2.3.3 SN74HCS72 and TMUX1219
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Altium Project
      4. 4.1.4 Assembly Drawings
        1. 4.1.4.1 Gerber Files
    2. 4.2 Documentation Support
    3. 4.3 サポート・リソース
    4. 4.4 Trademarks
  10. 5About the Author

3.2 Test Setup

To test the zero-cross detection reference design it is recommended to connect an oscilloscope to EN, SEL, a differential probe to the AC source, and a current probe to the load. Connect a 5-V power source and ensure that the TPSI3050-Q1 has powered up by measuring VDDH (10-V) and VDDM (5-V). Finally, connect the AC source and load to test the design. The circuit should look as Figure 3-1.

Table 3-1 Test Points and Connectors
Name Description
J1, TP2 SW1 AC source connection
J2 USER_EN External signal to control TPSI3050-Q1 EN signal
VDDP Power supply for primary side
VSSP Ground supply for primary side
J3 Power transfer selection
J4, TP9 SW2 Load connection
J5 USER_EN External signal to control TPSI3050-Q1 EN signal without zero-cross detection
EN TPSI3050-Q1 Active high driver enable
ZCD_EN Zero-cross switching enable signal to control TPSI3050-Q1
J6 SWITCH_SEL Signal to control the output of the multiplexer using switch (S1)
SEL Signal to control the output of the multiplexer
USER_SEL External signal to control the output of the multiplexer
TP1 VDDP TPSI3050-Q1 Power supply for primary side
TP3 VDRV TPSI3050-Q1 Active high driver output
TP4 VG Gate voltage of the power switches
TP5 EN TPSI3050-Q1 Active high driver enable
TP6 VDDH TPSI3050-Q1 Generated high supply
TP7 PXFR TPSI3050-Q1 Increase or decrease power transfer
TP8 VDDM TPSI3050-Q1 Generated mid supply
TP10, TP11 VSSS Ground supply for secondary side
TP12, TP13, TP17 VSSP Ground supply for primary side
TP14 SEL

Multiplexer output select signal
TP15 OUT2_CLK Output of the isolated comparator
TP16 USER_SEL External signal to connect to SEL

Steps to Test the Reference Design

  1. J3 connector should be connecting R3 (20 kΩ). This allows for the highest power transfer.
  2. J5 connector should be connecting ZCD_EN to EN. This allows the TPSI3050-Q1 to be controlled by the zero-cross detection logic.
  3. J6 connects SWITCH_SEL or USER_SEL to the SEL signal of the multiplexer. For this test, an external signal (USER_SEL) is provided to control the multiplexer output.
  4. Connect 5-V supply to VDDP.
  5. Check that VDDM and VDDH rails are 5-V and 10-V respectively.
  6. Connect AC source with a load.
Figure 3-1 Test Setup