JAJU882A December   2022  – January 2023

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Description of Control Logic
      2. 2.2.2 Behavior Throughout Charge Cycle
      3. 2.2.3 Additional Design Recommendations
      4. 2.2.4 Simulation Results
    3. 2.3 Highlighted Products
      1. 2.3.1 TPSI3052-Q1
      2. 2.3.2 TLV7011
      3. 2.3.3 UCC27517A-Q1
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 サポート・リソース
    4. 4.4 Trademarks
  10. 5About the Authors
  11. 6Revision History

2.2.1 Description of Control Logic

For simplicity, EN and VDDP signals are both connected to the same supply and both are provided simultaneously. Before VDDP and EN signal are provided, M1 is opened and the inductor is disconnected from the system. When VDDP and EN are provided, TPSI3052-Q1 begins to transfer power to the secondary side and after VDDH is above its UVLO, then precharging begins. TLV7011 comparator and UCC27517A-Q1 driver are powered from the TPSI3052-Q1 device. The hysteresis comparator is explained in detail in the Comparator with Hysteresis Reference Design reference design. The comparator can be considered as a hysteresis comparator with VTH (high threshold) and VTL (low threshold). With the following conditions.

- V (RSHUNT) = VH → TLV7011 outputs 0 V → FET OFF

- V (RSHUNT) = VL → TLV7011 outputs 5 V → FET ON

The voltage across RSHUNT can be determined as I✕R. Essentially the current to the inductor is controlled by the voltage across RSHUNT. The hysteresis comparator is described with the following equations. It is recommended to select R2 > 10 kΩ to minimize the current draw of the circuit.

Equation 6. R 2 R 1   =   V L V H   -   V L
Equation 7. R 3 R 1   =   V L +5 V _ V i s o   -   V H
Equation 8. V H   =   I P E A K   ×   R S H U N T
Equation 9. V L   =   I M I N   ×   R S H U N T

VL = falling hysteresis threshold which determines IMIN

VH = rising hysteresis threshold which determines IPEAK

+5V_Iso = 5-V VDDM supply from TPSI3052-Q1 powering TLV7011

RSHUNT = Shunt resistor for current sensing

TPSI3052-Q1 provides power to the control circuitry, but has limited power transfer capability. Aim to reduce the current draw from the control circuitry so that power can be allocated to the charging and discharging of the FET gate during switching at the desired switching frequency. Equations 6 and 7 show the relation between switching frequency, drive current, drive voltage, and total gate charge.

Equation 10. I D R I V ER_MAX   =   Q g   ×   F M A X
Equation 11. P D R I V ER_MAX   =   I D R I V ER_MAX   ×   V D R I V ER

FMAX = maximum switching frequency required for the active precharge

IDRIVER_MAX = maximum driver current when the switching frequency is FMAX

PDRIVER_MAX = maximum power demand to achieve the expected FMAX