2 Sharing the Control Bus

The TLV320ADCx140/PCMx140-Q1 devices are controlled through an I²C bus operating in standard mode, fast mode, and fast mode plus. This I²C control bus requires a 7-bit slave address whose two least significant bits are programmable by pulling the ADDR0_SCLK and ADDR1_MISO pins to VSS or IOVDD. By programming different I²C slave addresses through these pins, several TLV320ADCx140/PCMx140-Q1 devices can share a single I²C control bus. Moreover, a programmable broadcast enable feature allows you to temporarily change the I²C slave address to 1001100 for TLV320ADCx140/PCMx140-Q1 . This temporary slave address allows for simultaneous broadcasting I²C communication to all TLV320ADCx140/PCMx140-Q1 devices in the system. Table 2-1 lists the four possible TLV320ADCx140/PCMx140-Q1 device addresses resulting from these pin and broadcast configuration options. In these table entries for ADDR1_MISO and ADDR0_SCLK, the notation '0' refers to pulling the pin to VSS, while notation '1' refers to pulling the pin to IOVDD. The notation 'X' refers to pulling the pin to either VSS or IOVDD.

The dual- channel TLV320ADCx120/PCMx120-Q1 devices do not include address pins and thus have a fixed 7-bit I2C slave address of 1001110. The TLV320ADCx120/PCMx120-Q1 also supports the I2C broadcast mode and when the I2C_BRDCAST_EN (P0_R2_D2) bit is enabled the address becomes 1001100 which allows for simultaneous communication to other TLV320ADCx140/PCMx140-Q1 devices in the system that may share the same bus.