SBAA401A July 2019 – January 2024 TLV320ADC3140 , TLV320ADC5140 , TLV320ADC6140
Two examples are presented below for configuring the AGC for two different target applications. Example 1 is for scenarios when the noise is much lower than the input signal. Example 2 is for scenarios where the noise is significantly larger than the desired signal.
Example 1: When noise is significantly smaller in amplitude compared to signal, the AGC can easily distinguish between noise and signal by setting the Noise Threshold higher than the noise floor, but lower than the weakest possible signal. When such clear demarcations are possible, higher maximum gain can be used, since there is low possibility of gaining up the noise. The following values can be used for this application.
# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 4-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2, INP3/INM3 - Ch3 and INP4/INM4 - Ch4
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
w 98 00 00 # Goto Page 0
w 98 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
w 98 02 81 # Exit Sleep mode
d 10 # Wait for 16 ms
w 98 6C 48 # Enable AGC in DSP_CFG1
w 98 3C 01 # Select AGC on Ch. 1 using CH1_CFG0
w 98 41 01 # Select AGC on Ch. 2 using CH2_CFG0
w 98 74 01 # Select AGC on Ch. 3 using CH3_CFG0
w 98 75 01 # Select AGC on Ch. 4 using CH4_CFG0
w 98 70 E7 # AGC LVL = -36 dB, AGC GAIN = 24 dB
w 98 00 05 # Goto Page 5
w 98 7C 7F B5 16 50 # AGC Release Time Alpha
w 98 00 05 # Goto Page 6
w 98 08 00 4A E9 B0 # AGC Release Time Beta
w 98 0C 50 FC 64 5C # AGC Attack Time Alpha
w 98 10 2F 03 9B A4 # AGC Attack Time Beta
w 98 18 00 00 02 00 # AGC Attack Debounce
w 98 1C 00 04 B0 00 # AGC Release Debounce
w 98 20 FF FF A6 00 # AGC Noise Threshold : -90 dB
w 98 44 00 04 B0 00 # AGC Noise Debounce
w 98 3C 00 00 01 00 # AGC Attack Hysteresis
w 98 34 00 00 03 00 # AGC Release Hysteresis
w 98 54 00 00 04 00 # AGC Noise Hysteresis : 4 dB
w 98 78 7F 7F D2 B4 # AGC HPF B0
w 98 7C 80 80 2D 4C # AGC HPF B1
w 98 00 06 # Goto Page 6
w 98 54 7E FF A5 68 # AGC HPF A1
w 98 00 00 # Goto Page 0
w 98 07 30 # TDM Mode with 32 Bits/Channel
w 98 73 f0 # Enable Ch.1 - Ch.4
w 98 74 f0 # Enable ASI Output channels
w 98 75 e0 # Power up ADC
Example 2: When noise is significantly high and not easily distinguishable from a weak signal, it is not recommended to use a high maximum gain. The Noise Threshold has to be set closer to the expected noise floor. The following values can be used for this application.
# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 4-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2, INP3/INM3 - Ch3 and INP4/INM4 - Ch4
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
w 98 00 00 # Goto Page 0
w 98 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
w 98 02 81 # Exit Sleep mode
d 10 # Wait for 16 ms
w 98 6C 48 # Enable AGC in DSP_CFG1
w 98 3C 01 # Select AGC on Ch. 1 using CH1_CFG0
w 98 41 01 # Select AGC on Ch. 2 using CH2_CFG0
w 98 74 01 # Select AGC on Ch. 3 using CH3_CFG0
w 98 75 01 # Select AGC on Ch. 4 using CH4_CFG0
w 98 70 E5 # AGC LVL = -36 dB, AGC GAIN = 18 dB
w 98 00 05 # Goto Page 5
w 98 7C 7F B5 16 50 # AGC Release Time Alpha
w 98 00 05 # Goto Page 6
w 98 08 00 4A E9 B0 # AGC Release Time Beta
w 98 0C 50 FC 64 5C # AGC Attack Time Alpha
w 98 10 2F 03 9B A4 # AGC Attack Time Beta
w 98 18 00 00 02 00 # AGC Attack Debounce
w 98 1C 00 04 B0 00 # AGC Release Debounce
w 98 20 FF FF AC 00 # AGC Noise Threshold : -84 dB
w 98 44 00 04 B0 00 # AGC Noise Debounce
w 98 3C 00 00 01 00 # AGC Attack Hysteresis
w 98 34 00 00 03 00 # AGC Release Hysteresis
w 98 54 00 00 04 00 # AGC Noise Hysteresis : 4 dB
w 98 78 7F 7F D2 B4 # AGC HPF B0
w 98 7C 80 80 2D 4C # AGC HPF B1
w 98 00 06 # Goto Page 6
w 98 54 7E FF A5 68 # AGC HPF A1
w 98 00 00 # Goto Page 0
w 98 07 30 # TDM Mode with 32 Bits/Channel
w 98 73 f0 # Enable Ch.1 - Ch.4
w 98 74 f0 # Enable ASI Output channels
w 98 75 e0 # Power up ADC