SBAA495A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 I2S and LJF Standard Bus Formats
    2. 3.2 Support for Non-Standard I2S and LJF Bus Formats
  6. 4Related Documentation
  7.   A Revision History

3.2 Support for Non-Standard I2S and LJF Bus Formats

TLV320ADCx120 and PCMx120-Q1 devices can also support non-standard I2S and LJF bus formats through the configurable option in the following registers:

  • BCLK_POL (Page 0, ASI_CFG0 Register 0x07, Bit 2)
  • TX_EDGE (Page 0, ASI_CFG0 Register 0x07, Bit 1)
  • FSYNC_POL (Page 0, ASI_CFG0 Register 0x07, Bit 3)
  • TX_OFFSET (Page 0, ASI_CFG1 Register 0x08, Bit 4-0)
  • INV_BCLK_FOR_FSYNC (Page 0, CLK_SRC Register 0x16, Bit 1)

Figure 3-3 and Figure 3-4 depict examples for the non-standard I2S and LJF bus formats that can be achieved using the following register settings:

  • BCLK_POL (Page 0, ASI_CFG0 Register 0x07, Bit 2) = 1
  • TX_EDGE (Page 0, ASI_CFG0 Register 0x07, Bit 1) = 1
GUID-203E80C9-DBE2-483B-883F-03CEC5EDA62A-low.gifFigure 3-3 Custom I2S Format in Controller Mode (TX_OFFSET = 0)
GUID-F2C10A55-5085-4A9D-AA1D-0434EA3E4DEE-low.gifFigure 3-4 Custom LJF Format in Controller Mode (TX_OFFSET = 0)